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technical reference manual usar ACPITROLLER? 342 system management family ur8hc342 hid & acpi embedded controller confidential preliminary document number: doc8-342-tr-080 date: september 2000 ? 1999-2000 usar ? a semtech company a semtech company
usar ? a semtech company intellectual property disclaimer this specification is provided ?as is? with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. a license is hereby granted to reproduce and distribute this specification for internal use only. no other license, expressed or implied to any other intellectual property rights is granted or intended hereby. authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights. all other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
ACPITROLLER? basic ur8hc342 preliminary system management controller product table of contents usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential toc-1 table of contents chapter 1 / introduction document revisions 1-1 overview 1-3 scope of this document 1-4 features at a glance 1-5 pin overview 1-6 pin usage 1-7 pin description 1-8 usar ACPITROLLER? sample configuration 1-11 chapter 2 / human input device controller interface hidc bus interface 2-1 usar ACPITROLLER? hidc registers 2-2 hidc commands 2-5 ps/2 information registers 2-12 chapter 3 / alphakey? keyboard manager overview 3-1 usar alphakey? features at a glance 3-3 usar alphakey? hardware configuration 3-3 ps/2 keyboard protocol command and data handling 3-6 usar alphakey? keyboard matrix 3-8 usar alphakey? key numbers 3-9
ACPITROLLER? basic ur8hc342 preliminary system management controller product table of contents usar ? a semtech company toc-2 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company chapter 4 / alphamouse? pointing devices manager overview 4-1 multiplex mode 4-2 legacy mode 4-3 chapter 5 / embedded controller interface ur8hc342 ec bus interface 5-1 ur8hc342 embedded controller registers 5-2 port operation 5-4 ec commands 5-6 chapter 6 / sci & swi interrupt generation event interrupts 6-1 interrupt generation 6-4 chapter 7 / smbus host controller interface overview 7-1 smbus overview 7-1 the smbus host controller interface 7-1 smbus alarm message & smbus alert process 7-2 smbus error recovery 7-3 smbus host register space 7-3 smbus host registers 7-3 chapter 8 / general input/output options internal virtual smbus device 8-1
ACPITROLLER? basic ur8hc342 preliminary system management controller product table of contents usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential toc-3 gio0: led driver 8-3 gio1: analog output for flat panel digital controls 8-5 gio2: 3-channel 10-bit analog to digital converter 8-10 gio3: general purpose i/o 8-12 chapter 9 / electrical characteristics absolute maximum ratings recommended operating conditions / electrical characteristics ? digital section recommended operating conditions / electrical characteristics ? analog section chapter 10 / sample schematic appendix a usar alphakey? standard ps/2 key number definitions a-1 appendix b usar alphakey? default keyboard matrix and layout b-1 appendix c standard smbus registers c-1 standard smbus protocol c-6
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ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-1 introduction document revisions document revision history date version comments 1999/07/28 0.60 initial draft 1999/09/14 0.70 incorporated technical corrections and clarifications; grayed out features that are still in development 2000/09/11 0.80 incorporated technical corrections and clarifications
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-2 this page intentionally left blank
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-3 usar ACPITROLLER? technical reference introduction overview the ur8hc342 is a single ic that functions both as an 8042-type human input device controller (hidc) and an acpi-compliant embedded controller (ec). the ur8hc342 provides the typical functionality of an 8042-type hid controller with embedded key and motion scanning. in addition, the ur8hc342 functions as an acpi compliant embedded controller (ec) and smbus host. the ic achieves unparalleled minimum power consumption (typically less than 1 a) due to usar?s patented zero-power? technologies for both ps/2 ports and the smbus port ? an industry first. the usar ACPITROLLER? can power down even when devices are connected and active. based on usar?s patented zero-power? technology, the ur8hc342 always operates in the ?stop? mode, independently of the configuration and without any data or event losses. the usar alphakey? keyboard manager, implemented in the ur8hc342, provides oems with the most advanced and versatile keyboard management functions, including keyboard matrix programming. the usar alphamouse? pointing device manager supports mousewheel operation, recommended by microsoft, for both the embedded and the hot- plugged external pointing devices. using the ur8hc342, system designers can implement systems that take advantage of the smbus, the smart battery system, and the acpi specifications, all using a single ic. the ur8hc342 uses usar?s patented zero-power? smbus technology and is the lowest power consumption ic in the market today. the ur8hc342 can be customized easily through an extensive library of hardware and firmware modules in order to accommodate specialized configurations at low production cost. smbus host the ic manages one hardware smbus port. the ic complies with version 1.0 of the smart battery system (sbs) and smbus specifications.
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-4 scope of this document this is a preliminary document. although all the functions described in this document have been tested in usar?s laboratories, the document may contain errors and inaccuracies. prior to committing to design, consult with usar for up to date revisions. some features described in this document are still in development; these features are identified by grayed-out text . usar has used every effort to design the part in the best manner to serve the current industry needs. nevertheless, input from oems for both function and configuration is appreciated and may result in future modifications and enhancements. this document is still in a confidential state, as printed on the bottom of each page, and it cannot be distributed without explicit permission from usar. please forward all your comments or questions regarding this product and document to: acpi@usar.com usar systems, inc. 568 broadway new york, ny 10012 212.226.2042 telephone 212.226.3215 telefax evaluation kits for information or to order a usar ACPITROLLER? evaluation kit, send your email to: info@usar.com
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-5 features at a glance ? typical power consumption of less than 1 a as a result of usar?s patented zero-power? technologies; the ic can power down even when devices are connected and active ? patented zero-power? operation of all ps/2 ports and the smbus port ? an industry first ? alphamouse? pointing device manager supports hot-plugging and hot- swapping of standard two-button and three-button mice without a special driver; it also supports hot-plugging and hot-swapping of mousewheel mice with a mousewheel-capable driver ? two external ps/2 ports for external keyboard and mouse with auto-detect and hot-plug support ? simultaneous operation of external and internal input devices ? support of mousewheel functionality for both embedded and external pointing devices, even with hot-plug connections, with a mousewheel- capable driver ? 8042-compatible host interface and functionality ? 8 x 16 fully programmable scanned keyboard matrix ? support of all three keyboard scan code sets ? acpi ec host interface ? support of up to 6 acpi gpe interrupt inputs ? acpi power button and power button override support ? smbus compatible host complies with version 1.0 of the sbs/smbus specifications ? blocks potentially dangerous smart battery system commands (write charger voltage and write charger current) issuing from the host system ? up to three 10-bit a/d inputs ? two d/a and two pwm outputs ? easily customized for specialized applications ? three-volt and five-volt operation ? alphamouse? performs active ps/2 multiplexing of input from different types of mice simultaneously, with the appropriate driver(s) ? support of the usar screencoder? ps/2 absolute and relative touchscreen encoder, with the appropriate driver ? support of the five-button mouse, with an appropriate driver
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-6 pin overview the figure below illustrates the pins for the ur8hc342 implementation for the fq package. 1 80 61 20 21 40 41 60 ivsd20/an0 scl0 sda0 ps21clk ps20clk imclk ps21dat ps20dat imdat gio13/da2/pwm2 gio12/da1/pwm1 gio37/gpe7/dock gio36/gpe6/lid iow ior 8042s a2 acpis sci kbinit a20gate irq12 irq1 cnvss reset syssus swi xin xout vss gio03/katakanaled gio02/cap_lock gio01/num_lock igio00/scroll_lock row3 row2 row1 row0 col15 col14 gio11/pwm2/gpe1 gio10/pwm1/gpe0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 vcc vref avss row7 row6 row5 row4 smben gio22/an2 gio21/an1 gio32/gpe2/pwbutton gio33/gpe3/pwboverride gio34/gpe4 gio35/gpe5 smbint keywkup col0 col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 urhc342-
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-7 pin usage
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-8 pin description the following table describes the pins of the usar ur8hc342 ACPITROLLER?. note: if a pin is active low, then there is an overscore over the pin name in schematics, and there is a single underscore character (_) preceding the pin name in tables and text; for example, _reset. ACPITROLLER ? pin descriptions pin name pin no. description power supply avss 73 analog signal ground cnvss 24 should be tied to ground vcc 71 vcc 3-5 volts vref 72 analog circuitry reference voltage vss 30 ground oscillator pins xin 28 oscillator input (8 mhz operating frequency) xout 29 oscillator output reset _reset 25 controller hardware reset pin system bus interface pins _8042s 16 8042 keyboard controller port select signal input _acpis 18 acpi embedded controller port select signal input _ior 15 x-bus/isa i/o read signal input _iow 14 x-bus/isa i/o write signal input irq1 23 keyboard interrupt output irq12 22 mouse interrupt output _kbinit 20 keyboard initialize output a2 17 x-bus/isa address 2 input a20gate 21 a20 gate output signal dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 70 69 68 67 66 65 64 63 x-bus/isa parallel data i/o ports
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-9 ACPITROLLER ? pin descriptions pin name pin no. description acpi, smbus, and general purpose i/o signals sci 19 system control interrupt output _smbint 56 smbus interrupt input _swi 27 system wake-up event interrupt output _syssus 26 system suspend input gio00 /scroll_lock 34 this pin can be programmed to act as a keyboard led or as a gpio pin. gio01/num_lock 33 this pin can be programmed to act as a keyboard led or as a gpio pin. gio02/cap_lock 32 this pin can be programmed to act as a keyboard led or as a gpio pin. gio03 /katakanaled 31 this pin can be programmed to act as a keyboard led or as a gpio pin. gio10/pwm1/gpe0 62 gio1 bit 0 or pwm output or acpi gpe gio11/pwm2/gpe1 61 gio1 bit 1 or pwm output or acpi gpe gio12/da1/pwm1 11 this pin can be configured as gpio, as d/a output, or pwm output. gio13/da2/pwm2 10 this pin can be configured as gpio, as d/a output, or pwm output. gio20/an0 1 this pin can be configured as a 10-bit a/d input or logic i/o. gio21/an1 80 this pin can be configured as a 10-bit a/d input or logic i/o. gio22/an2 79 gio2 bit or a/d input gio36/gpe6/lid 13 gio3 bit 0 or acpi general purpose event (gpe); capable of detecting both negative and positive signal transitions; typically serves the lid acpi function gio37/gpe7/dock 12 gio3 bit 1 or acpi gpe; capable of detecting both negative and positive signal transitions; typically serves the dock acpi function gio32/gpe2 /_pwbutton 60 gio3 bit 2 or acpi gpe; typically an acpi ""power button"" input. gio33/gpe3 /_pwboverride 59 gio3 bit 3 or acpi gpe; typically an acpi ""power button override"" input gio34/gpe4 58 gio3 bit 4 or acpi gpe 4 gio35/gpe5 57 gio3 bit 5 or acpi gpe 5 scl0 2 this pin acts as the clock line for the smbus sda0 3 this pin acts as the data line for the smbus
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-10 ACPITROLLER ? pin descriptions pin name pin no. description acpi, smbus, and general purpose i/o signals smben 78 this output pin allows the smbus latch to notify the ACPITROLLER? when smbus activity has been detected. it is used to wake the ACPITROLLER? from sleep mode, and to disable all ps/2 inputs while smbus processing is taking place. scanned matrix pins col0 col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 column matrix outputs keywkup 55 key wake-up output row0 row1 row2 row3 row4 row5 row6 row7 38 37 36 35 77 76 75 74 row matrix inputs ps/2 ports imclk 6 ps/2 clock line for internal mouse imdat 9 ps/2 data line for internal mouse ps20clk 5 clock line for external ps/2 port 0; both external ps/2 ports support hot-plug ins and auto-select for keyboard or mouse ps20dat 8 data line for external ps/2 port 0 ps21clk 4 clock line for external ps/2 port 1 ps21dat 7 data line for external ps/2 port 1
ACPITROLLER? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-11 usar ACPITROLLER? sample configuration the usar ACPITROLLER? is a highly versatile part that can be configured to accommodate different oem configurations. the block diagram below illustrates the major functional components of the usar ACPITROLLER? in a simple configuration. usar ACPITROLLER ? sample configuration embedded controller ec data register ec control/status acpi ec registers smbus host 3 x ps/2 ports 8 x 16 matrix eyboard controller kbc data register kbc control/statusb 8042 kbc registers sci smbint 8 d0-d7 irq1 irq12 kbinit a20gate acpis 8042s iow, ior, a2 4 swi smben 2 10 bit a/d d/a, pwm 2 brightness/ contrast a/d pio gpio 4 bit port expander gio0 gio2 gio1 gpe gio3 2 smbus 4 gpex pwbutton pwboverride simple configuration block diagram of ur8hc342 in the configuration shown above the usar ACPITROLLER ? is configured to provide besides the basic ec and kc functionality the following: ? power button and power button override function implemented on gpe pins ? 4 general-purpose i/o pins ? 4 additional gpe inputs ? 3 pins that can be configured as 10 bit a/d channels or gpio ? 2 pins that can be configured as d/a or pwm outputs or gpio ? one zero-power ? smbus port
ACPITROLLER ? basic ur8hc342 preliminary system management controller product introduction usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 1-12 this page intentionally left blank
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-1 doc8-342-tr-080 confidential usar ACPITROLLER? human input device controller (hidc) interface hidc bus interface the human input device controller (hidc) portion of the usar ACPITROLLER? interfaces to the host isa bus via two i/o addresses, generally 0x60 and 0x64. the following diagram illustrates the hidc register architecture. usar ACPITROLLER? hid controller interface hidc data input register (60h) hidc data output register (60h) hidc command/status register (64h) 8042 hid controller ram register and expanded program memory isa data write data read status read command write kbd interrupt mouse interrupt gate a20 hidc reset
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-2 doc8-342-tr-080 confidential usar ACPITROLLER? hidc registers the hidc portion of the usar ACPITROLLER? contains three registers that occupy two i/o locations. the registers are listed in the following table: hidc registers name description i/o function i/o port address hidc_sc(w) command iow 0x64 hidc_sc(r) status ior 0x64 hidc_data data ior/iow 0x60 hidc status register, hidc_sc (r) the hidc status register is a read-only register that indicates the current status of the keyboard controller interface. it contains the following fields: hidc_sc (r) status register bit definitions bit7 bit6 bit5 bit4 hidc_pe hidc_gto hidc_aobf hidc_inh bit3 bit2 bit1 bit0 hidc_cmd hidc_sf hidc_ibf hidc_obf
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-3 doc8-342-tr-080 confidential hidc_sc (r) status register bit descriptions hidc_pe parity error 1 ? indicates a parity error. in this case 0xff is placed in the data register 0 ? indicates that the last byte of data received from the ps/2 device had odd parity hidc_gto general time-out 1 ? indicates that a time-out occurred during a transaction with one of the ps/2 devices. the hidc_gto is set in any of the following situations: ? reception of a byte from a ps/2 device started but did not complete within the receive time out limit. the hidc places 0xff into the data register ? a transmission started by the hidc to a ps/2 device, but was not completed within the transmit time out limit. the hidc places 0xfe into the data register ? a byte requiring response (command) was clocked out to a ps/2 device but it was not acknowledged within the ack time limit ? a command byte was clocked out and a response was received with a parity error. in this case both hidc_gto and hidc_pe are set 0 ? no time-out hidc_aobf auxiliary output buffer full this bit works in conjunction with hidc_obf (output buffer full) bit 1 ? when hidc_obf is also set, indicates that data from the auxiliary device is pending in the data register 0 ? when hidc_obf is set, indicates that keyboard data or a hidc response is pending in the data register hidc_inh inhibit switch 1 ? keyboard is enabled 0 ? password state is active and the keyboard is inhibited (for more information, see section below on password protection) hidc_cmd command/data 1 ? data register contains a command byte (set by the host, read by the hidc) 0 ? data register contains a data byte (set by the host, read by the hidc) hidc_sf system flag 1 ? the system flag bit in the controller command byte is set to one 0 ? the system flag bit in the controller command byte is set to zero (default after reset) hidc_ibf input buffer full 1 ? input buffer is full (data has been written in the data register but has not been read by the hidc) 0 ? input buffer is empty (data has been read by the hidc) hidc_obf output buffer full 1 ? data ready for host in the data register (generate appropriate interrupt) 0 ? data has been read by the host (set automatically after an io read operation) command register, hidc_sc (w) the hidc_sc (w) command register is a write-only register that allows commands to be issued to the keyboard controller. write operations to this port are latched into the input data register; the input buffer full (hidc_ibf) flag is set in the status register. writes to this location also cause the hidc_cmd (command/data) bit to be set in the status register. this
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-4 doc8-342-tr-080 confidential enables the keyboard controller to differentiate the start of a command sequence from a data byte write operation. data register, hidc_data(r/w) the hidc_data(r/w) data register is a read/write register that allows command/data bytes to be issued to the keyboard controller while also enabling the host system to read data returned by the keyboard controller. writes to this port are latched into the input data register; the input buffer full (hidc_ibf) flag is set in the status register. data written by the system into this register is generally transmitted to the appropriate ps/2 device, unless the hidc expects a data byte as part of a command sequence. reads from this register return data from the output data register and clear the output buffer full (hidc_obf) flag in the status register.
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-5 doc8-342-tr-080 confidential hidc commands any byte written by the host system into the hidc_sc register is interpreted as a command. the usar ACPITROLLER? supports all the standard 8042 commands, as well as expanded commands, as described below. standard 8042 commands hex value description 20 read controller command byte 21-3f read hidc ram registers. address is specified by bit0-bit5 60 write controller command byte. the following byte is data 61-7f write hidc ram registers. address is specified by bit0-bit5, and the following byte is data a4 test password installed. the result is placed in the data buffer as follows: ? 0xfa ? installed ? 0xf1 ? not installed (see below) a5 load password. data follows until a null (0) is detected (see below) a6 enable password. this command is valid only when a password is loaded in the controller (see below) a7 disable auxiliary device interface. this command sets bit 5 of the controller command byte and disables the auxiliary device clock line a8 enable auxiliary device interface. this command clears bit 5 of the controller command byte and enables the auxiliary device clock line a9 auxiliary device interface test. test results are returned in the data buffer as follows: ? 00 ? no error ? 01 ? clock line stuck low ? 02 ? clock line stuck high ? 03 ? data line stuck low ? 04 ? data line stuck high aa controller self test, return 55. ab keyboard device interface test. test results are returned in the data buffer as follows: ? 00 ? no error ? 01 ? clock line stuck low ? 02 ? clock line stuck high ? 03 ? data line stuck low ? 04 ? data line stuck high ad disable keyboard interface. this command sets bit 4 of the controller command byte and disables the keyboard clock line ae enable keyboard interface. this command clears bit 4 of the controller command byte and enables the keyboard clock line c0 read input port and place data in the data register c2-c3 poll input port and update bit7-bit4 of the status register d0 read output port and place data in the data register d1 write output port. the next byte is written to the hidc output port d2 write keyboard output buffer. the next byte is played back as if originating from the keyboard d3 write auxiliary device output buffer. the next byte is played back as if originating from the auxiliary device
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-6 doc8-342-tr-080 confidential standard 8042 commands hex value description d4 write to auxiliary device. the next byte is transmitted to the auxiliary device e0 read test inputs. returns 0 (type 1 controller) f0-ff pulse output port. this command pulses output port bits, defined by bit0- bit3, for approximately 6 us. keyboard password the usar ACPITROLLER? supports keyboard password functionality. there are three commands associated with the password operation. ? load password (0xa5) ? test password installed (0xa4) ? enable password (0xa6) the password can be loaded into the usar ACPITROLLER? ram area by the system at any time, using the ?load password? command. the password can be up to seven bytes long and is loaded using scan code 1 (scan codes provided by the system). the system can check if a password is installed using the ?test password installed? command. if a password is already installed, the system can enable the password by issuing the ?enable password? command. while the password is enabled, the hidc enters the secure mode and behaves as follows: 1. the hidc intercepts any incoming code stream from the keyboard and compares it with what is installed in the ram password pattern. the hidc discards any code from the keyboard and the auxiliary device that does not match the password. if an incoming code does not match either the next character in the pattern or the contents of ram register addresses 0x16 and 0x17, the hidc resets its password pointer and the next incoming code is compared to the first byte of the password pattern. 2. while in secure mode, the hidc does not pass any codes to the system or accept any commands. 3. after a match occurs, the hidc resumes normal operation and starts passing codes to the host system.
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-7 doc8-342-tr-080 confidential there are four hidc ram registers related to the password operation: password associated ram registers ram register address description security on 13h when the password is enabled, a non-zero value in this register forces the hidc to output the contents of the register into the data register and issue irq1 security off 14h when the password is matched, a non-zero value forces the hidc to output the register contents into the data register and issue irq1 make 1 & 2 16h, 17h these registers can be loaded by the system with scan codes that should be ignored during the password match process (i.e., shift codes) hidc ram registers the hidc has on-board ram registers, listed in the table below. hidc ram registers are accessed for read and write operations through the read/write hidc ram register commands. a description of specific ram registers follows. hidc ram registers address offset description of register 00 controller command byte (read or write) 01-12 not defined, system use 13 security on 14 security off 16-17 make 1 and 2
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-8 doc8-342-tr-080 confidential controller command byte the controller command byte occupies address offset zero in the hidc ram register space. the controller command byte can be accessed through general read/write or specific commands and contains the following bits: controller command byte bit definitions bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 res trs adis kdis res sf airq kirq controller command byte bits descriptions res reserved trs keyboard translate 1 ? sets keyboard translation from scan code set 2 to scan code set 1 0 ? disables keyboard scan code translation adis disable auxiliary device 1 ? hidc disables the auxiliary device by pulling the clock line low 0 ? hidc enables the auxiliary device kdis disable keyboard 1 ? hidc disables the keyboard by pulling the clock line low 0 ? hidc enables the keyboard sf system flag the value written in this bit is placed in the relevant bit of the status register (system use) airq enable auxiliary device interrupts setting this bit to 1 enables irq12 whenever an auxiliary device data byte is placed into the data register kirq enable keyboard interrupts setting this bit to 1 enables irq1 whenever a keyboard data byte is placed into the data register
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-9 doc8-342-tr-080 confidential security on the security on register is used for keyboard password functionality. when the password is enabled, a non-zero value in this register forces the hidc to output the contents of the register into the data register and issue irq1. security off the security off register is used for keyboard password functionality. when the password is matched, a non-zero value forces the hidc to output the register contents into the data register and issue irq1. make 1 and 2 these registers are used for keyboard password functionality and can be loaded by the system with scan codes that should be ignored during the password match process (i.e., shift codes). alphakey? control register alphakey? control register alphakey? control register alphakey? control register this register controls local handling of the ps/2 keyboard protocol, defines pins as gpio or keyboard leds, and enables and disables programming of the embedded keyboard matrix. functional details are described in full in the alphakey ? keyboard manager chapter.
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-10 doc8-342-tr-080 confidential hidc usar expanded command set in addition to the standard 8042 commands, the hidc section implements a set of expanded commands, defined by usar in order to accommodate the special functions implemented in the usar ACPITROLLER? hid section. these commands provide bios, drivers and application software with access to the following unique features of the usar ACPITROLLER?: ? version control ? oem programmable area ? scanned keyboard matrix programmability hidc expanded commands hex value description b0 read model number, 1byte bit7: ? 0: standard part ? 1: customized part bit6-bit0: model number a value of 01h denotes the basic configuration b1 read revision number, 1byte b2 write program ram page register valid values: 0, 1 b3 read program ram page register, 1 byte b4 write program ram pointer register valid values: 0 ? ffh for page 0; 0 ? 7fh for page 1; b5 read program ram pointer register, 1 byte b6 write to program ram in given page and current address b7 read from program ram in given page and current address b8 write data block to program ram, starting at specified address. this command is followed by one byte block size, one byte address and data b9 read from program ram by specified address ba download whole matrix layout0, follow by 128 bytes matrix bb download whole num lock and fn matrix layout, follow by 96 bytes matrix bc download whole macro function pointer, follow by 16 bytes pointer bd download whole macro function code, follow by 128 bytes code for commands b6 and b7, the ram pointer register automatically increments after each byte is read or written. the increment wraps from ffh to 00h within ram page 0 (you cannot implicitly write to page 1), and from 7fh to 00h within ram page 1. for the download commands (ba, bb, bc, and bd), you must issue the command in the command/status register, than send each byte of data, one at a time, in the data register. you must verify that the input buffer full bit (bit 1 of the hidc status register, as shown earlier in this chapter) has been cleared before sending the next byte. each of these commands expects a
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-11 doc8-342-tr-080 confidential fixed number of data bytes. the hidc must read all of the expected bytes before another command issues. if a new command issues before all expected bytes are read, the download command aborts and the rest of the matrix is unchanged.
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-12 doc8-342-tr-080 confidential ps/2 information registers starting at offset 15 from the start of the 8042 extended register area, there are three read-only registers with information about the three ps/2 ports: registers r15-r17. r15: 8042 configuration register 0 bit definitions (r) bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mxen res m3pend m2pend m1pend m3dis m2dis m1dis r15: 8042 configuration register 0 bit descriptions (r) res reserved mxen 1? mouse multiplexing mode enabled by command m3pend 1? mouse multiplexing mode command pending port 3 m2pend 1? mouse multiplexing mode command pending port 2 m1pend 1? mouse multiplexing mode command pending port 1 (internal) m3dis 1? direct port 3 clock disable by command m2dis 1? direct port 2 clock disable by command m1dis 1? direct port 1 clock disable by command r16: 8042 configuration register 1 bit definitions (r) bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ok2 kb2 5but2 wheel2 ok3 kb3 5but3 wheel3 r16: 8042 configuration register 1 bit descriptions (r) ok2 1? external device on port 2 initialized ok kb2 1? device on port 2 is a keyboard 0? device on port 2 is a mouse 5but2 1? device on port 2 is a 5-button mouse wheel2 1? device on port 2 is a wheel mouse ok3 1? external device on port 3 initialized ok kb3 1? device on port 3 is a keyboard 0? device on port 3 is a mouse 5but3 1? device on port 3 is a 5-button mouse wheel3 1? device on port 3 is a wheel mouse
ACPITROLLER? basic ur8hc342 preliminary system management controller product hid controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company 2-13 doc8-342-tr-080 confidential r17: 8042 configuration register 2 bit definitions (r) bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res res res res res ok1 5but1 wheel1 r17: 8042 configuration register 2 bit descriptions (r) res reserved ok1 1? internal device on port 1 initialized ok 5but1 1? device on port 3 is a 5-button mouse wheel1 1? device on port 3 is a wheel mouse
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ACPITROLLER? basic ur8hc342 preliminary system management controller product alphakey? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-1 usar ur8hc342 ACPITROLLER? alphakey? keyboard manager overview the usar alphakey? keyboard manager is the most advanced keyboard management module in the industry today and the first one to integrate the laptop keyboard matrix with system management tasks through acpi and smbus. the usar alphakey? keyboard manager provides oems with extreme flexibility both with ps/2 keyboard functionality, as well as with user control, from the keyboard, of system management tasks through acpi and smbus. the usar alphakey? keyboard manager, as shown in the following diagram, communicates with the hid controller, the acpi embedded controller, the virtual smbus device manager and the external ps/2 ports of the usar ACPITROLLER?. alphakey? communications block diagram the usar alphakey? keyboard manager can simultaneously support both an external keyboard (including windows ? and japanese layout keyboards) and an internal scanned key matrix. the internal scan matrix layout can be programmed through an extended set of keyboard commands. the usar alphakey? keyboard manager kbd mouse hid controller virtual smbus device manager acpi ec ps/2 ports leds keyboard matrix 4 r0-r7 c0-c15
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphakey? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-2 alphakey? keyboard manager handles ps/2 keyboard commands, supports external keyboard hot-plug-ins, and merges internal and external keyboard data as if they were coming from one source. usar alphakey? features at a glance ? supports ibm standard 101/102 keyboards including windows ? , on-now power keys, japanese keyboard keys , and korean keyboard keys . ? external keyboard and internal keyboard operate simultaneously; data is merged ? user can hot-plug external keyboard ? auto-detection of type of device in any external ps/2 port ? n-key rollover and ghost key detection ? programmable scan matrix ? embedded numeric keypad support ? supports all three scan code sets ? interoperability between 3-volt systems and 5-volt ps/2 devices without any external level-shifting circuitry ? unique ?zero-power ? ? operation of the scanned matrix and the ps/2 embedded port ? ?protocol safe? handling of external ps/2 devices
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphakey? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-3 usar alphakey? hardware configuration the usar alphakey? keyboard manager interfaces directly to the signals of the scanned matrix, the external ps/2 ports and the leds? port. this section describes the handling of the signal lines and the options oems have in configuring the hardware interfaces of the usar alphakey? keyboard manager. scanned matrix the usar alphakey? embedded keyboard is organized as an 8 x 16 matrix. while the maximum matrix size and the organization of rows and columns are fixed, smaller matrixes can be accommodated. the usar alphakey? matrix comes configured with a default key layout described in appendix b of this document. oems requiring a custom matrix layout are presented with the option to either order the ACPITROLLER? delivered with their own matrix specification or use the programming facilities of the usar ACPITROLLER?. configuration of the matrix layout can be accomplished though the usar extended command set of the hid controller (8042), and it is described in detail later in this section. custom configuration information is stored in the alphakey? ram and has to be downloaded into the controller each time power is re- cycled. alternatively, information can be stored permanently in the controller?s flash ram area ? if available ? or in a eeprom residing in one of the smbus ports of the controller.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphakey? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-4 led port the usar alphakey? keyboard manager supports up to four leds. three leds correspond to the standard 101/102 ps/2 keyboard numeric lock, caps lock and scroll lock leds. the fourth led is the katakana led used in japanese keyboards. oems have the option either to utilize the leds or to disable them in order to use the led port for other general input/output functions. the configuration of the led port is in the alphakey? control register, and it is described later in this section. external ps/2 ports the usar alphakey? supports three ps/2 ports, all of them functioning with usar?s patented ?zero-power?? operation. each of the three ps/2 ports is available for either a ps/2 keyboard or a ps/2 mouse-type device. the usar alphakey? keyboard manager detects the hot-plug-in of an external keyboard, and integrates its data input with the input from the embedded keyboard matrix. the usar alphakey? responds to and implements every ps/2 keyboard command, and individually handles communications with externally connected keyboard devices. in addition to this mode, the usar alphakey? can support a pure 8042 type of operation, in which the externally connected keyboard provides the responses to the system-issued ps/2 commands. this mode is implemented in order to support proprietary devices that identify themselves as ps/2 keyboards; however, they require special drivers in order to operate properly. setting the klhdis bit of the control register to one (1) activates the pure 8042 mode. while in this mode, only the first connected external ps/2 keyboard is enabled, in order to avoid conflicting responses from other devices to the custom driver.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphakey? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-5 auto-detection of device type in external ps/2 ports the usar ACPITROLLER? auto-detects the type of ps/2 device connected to either one of the two external ps/2 ports and configures the device properly according to the current system and driver settings. users can connect any type of ps/2 device (keyboard or mouse) to either port. data from any keyboard(s) detected are routed to the usar alphakey? keyboard manager for proper initialization and data handling. 3-volt and 5-volt operation of ps/2 ports the usar ACPITROLLER? can be powered by either a 3-volt or a 5-volt power supply. even when powered by a 3-volt power supply, the usar ACPITROLLER? communicates flawlessly with 5-volt powered ps/2 devices, without any additional level-shifting circuit.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphakey? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-6 ps/2 keyboard protocol command and data handling the usar alphakey? fully implements the ps/2 keyboard command protocol including support for scan code set 3 specific commands. support of scan code set 3 provides compatibility with all operating systems ported to the intel x86 architecture. the usar alphakey? keyboard manager, which responds to and executes all ps/2 keyboard. the table below lists the ps/2 commands supported by alphakey? as well as the corresponding responses to them. ps/2 command & response codes command response description ffh fah, aah keyboard reset command feh xxh resend last byte transmitted fdh, xxh fah, fah set key make (key) fch, xxh fah, fah set key make/break (key) fbh, xxh fah, fah set key typematic (key) fah fah set all keys typematic/make/break f9h fah set all keys make f8h fah set all keys make/break f7h fah set all keys typematic f6h fah set default f5h fah disable f4h fah enable f3h , xxh fah, fah set typematic delay and rate (value) f2h fah, 8xh, abh read device id f1h feh invalid command f0h, 00 ? 03 fah, fah, (0xh) set scan set (value) 0 = programmable keyboard matrix efh feh invalid command eeh eeh echo edh, 0xh fah, fah set leds (value)
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-7 protocol safe ? handling of external ps/2 keyboards the usar alphakey ? keyboard manager provides a level of protocol isolation between the external ps/2 keyboard(s) and the host system. even when an external keyboard is connected, commands issued by the system are responded to and executed internally within the usar alphakey ? keyboard manager. the usar alphakey ? keyboard manager subsequently relays only relevant commands to the external device(s) and it processes locally any hand-shaking, including errors and recovery messages. this unique mode of operation provides the system with two benefits: ? it isolates the system from bad implementations of the ps/2 keyboard protocol from external keyboards. the usar alphakey ? directs to the external keyboard only the simplest commands required for data entry and led handling and it handles internally the more complicated commands. it basically uses the external device the same way it handles the scanned matrix for pure key entry and it takes full responsibility of the protocol implementation. the system ? sees ? a consistent ps/2 keyboard protocol implementation independently of the ps/2 keyboard the user has connected to the external ps/2 ports. ? it improves the system performance. unlike keyboard controller implementations that rely on the external device to provide command responses, the usar alphakey ? communicates quickly and efficiently through the x-bus, and hides from the system the overhead of low level ps/2 error handling. usar alphakey ? scan code support usar ? s alphakey ? supports the ibm standard scan code sets 1, 2, and 3 for all keys, including windows ? and the on-now power keys (scan code 1 & 2 only).
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-8 usar alphakey ? keyboard matrix the usar alphakey ? implements three distinct key layouts over the same keyboard matrix. each keyboard matrix layout can be viewed as a separate keyboard selected and activated by the user through the fn and num lock key. the default layout is qwerty; this is the most commonly used layout, and it includes all keys needed for regular data entry. the numpad layout can be invoked by setting the num lock led on, and it implements a numeric keypad over part of the matrix for fast numeric entry. the fn layout is invoked when the user presses the fn key of the laptop keyboard, and it is used to activate special keys for system functions and custom data functions. the usar alphakey ? is preprogrammed with a typical laptop keyboard matrix, implementing all three layouts. the preprogrammed matrix and layouts are described in appendix b of this document. keyboard matrix layouts the usar alphakey ? keyboard manager maintains the keyboard matrix layout information in the controller ? s matrix ram area which is described later in this chapter. after a power-on reset, the usar alphakey ? defaults to scan set 1. subsequently, the oem can download a custom matrix and/or custom key definitions and assignments through bios, tsr programs or device driver software, and select scan set 0 to enable the custom matrix. the following table describes the matrix layouts supported by the usar alphakey ? . usar alphakey ? matrix layouts fn key num lock description up off qwerty layout up on numpad layout down x fn layout
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-9 usar alphakey ? key numbers the action invoked by a key press is determined primarily by the usar key number assigned to the specific matrix location. each matrix location has a usar key number assigned to it. if a matrix location is empty (no physical switch), or if the switch should produce no action in specific layouts, the null key number can be assigned into the specific position. usar has defined four distinct ranges of key numbers. the following table describes the usar defined key number ranges for keys supported by the alphakey ? keyboard manager. usar alphakey ? key number ranges key numbers (hex) no of keys category 00 - 7f 128 standard ps/2 keys 80 - af 48 alternate layout keys (numpad and fn layouts) a description of the codes in each of these ranges follows. standard ps/2 keys usar alphakey ? uses 128 unique numbers 00-7fh (0-127) to describe the standard ps/2 keys implemented in most standard ps/2 keyboard layouts. the key numbers for standard ps/2 keys are fixed and they are re-used. note the following special key ranges: 0 null key 1 - 101 101/102 keyboard keys 102 ? 104 windows keys. 105 overrun error 106 function (fn) key 107 sticky mode key. this key is used to toggle the ? sticky ? mode of operation of the ps/2 shift keys (ctrl, shift, alt, win keys) 108 ? 110 on-now power keys. 111 ? 115 japanese keyboard key numbers. korean keyboard key numbers. 124 ? 132 extended function keys f13 ? f24 a list of the usar standard ps/2 key numbers appears in appendix a of this document.
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-10 alternate layouts keys (numpad and fn layouts) the usar alphakey ? keyboard manager uses 48 distinct codes (80h ? afh) to describe a special range of keys that, in addition to their default qwerty values, implement the numpad and fn layout translations. each one of the ? alternate layouts ? keys has three key numbers associated with them which are programmable and kept in the matrix ram area of the controller. the output of an ? alternate layouts ? key is determined by the active matrix layout (qwerty, numpad or fn). oems can define the output for each layout to be a standard ps/2 key. the following drawings illustrate an example of an ? alternate layouts ? key. example 1: ?alternate layouts? key number dbh acts as the ?j? when the qwerty layout is active. example 2: the same key acts as the numeric keypad key ?1?, when the numpad layout is selected. backspace q w e r t y u i p o a s d f g h j k l z x c v b n m tab shift caps lock shift ctrl alt fn ctrl alt { [ } enter end pgdn pgup | \ home f1 esc f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 ! 1 ~ ` @ 2 # 3 $ 4 % 5 & 7 ^ 6 * 8 ( 9 ) 0 < , > . ? / : ; " ' _ - + = num lk scr lk insert prt sc delete sysrq pause break ] backspace q w e r t y u i p o a s d f g h 1 k l z x c v b n m tab shift caps lock shift ctrl alt fn ctrl alt { [ } enter end pgdn pgup | \ home f1 esc f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 ! 1 ~ ` @ 2 # 3 $ 4 % 5 & 7 ^ 6 * 8 ( 9 ) 0 < , > . ? / : ; " ' _ - + = num lk scr lk insert prt sc delete sysrq pause break ]
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-11 example 3: when the fn layout is active, the key acts as a ?null? key. backspace q w e r t y u i p o a s d f g h null k l z x c v b n m tab shift caps lock shift ctrl alt fn ctrl alt { [ } enter end pgdn pgup | \ home f1 esc f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 ! 1 ~ ` @ 2 # 3 $ 4 % 5 & 7 ^ 6 * 8 ( 9 ) 0 < , > . ? / : ; " ' _ - + = num lk scr lk insert prt sc delete sysrq pause break ]
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-12 the following table lists the default values of the ? alternate layouts ? keys. for each ? alternate layouts ? key number, three matrix ram locations exist to store its key number values for each matrix layout. the oem can program these ram locations, using the ? extended protocol ? commands. alternate layouts key numbers default values qwerty layout numpad layout fn layout alt. matrix matrix matrix layout key # (hex) ram offset (hex) usar key # (hex) key label ram offset usar key # (hex) key label ram offset (hex) usar key # (hex) key label 80 80 2f m a0 4a 0 / ins c0 2f m 81 81 23 j a1 41 1 / end c1 23 j 82 82 24 k a2 42 2 / down arrow c2 24 k 83 83 25 l a3 43 3 / pgdn c3 25 l d4 84 16 u a4 44 4 / left arrow c4 16 u 85 85 17 i a5 45 5 c5 17 i 86 86 18 o a6 46 6 / right arrow c6 18 o 87 87 08 7 / & a7 47 7 / home c7 08 7 / & 88 88 09 8 / * a8 48 8 / up arrow c8 09 8 / * 89 89 0a 9 / ( a9 49 9 / pgup c9 0a 9 / ( 8a 8a 19 p aa 4c num dash ca 19 p 8b 8b 26 /: ab 40 n.+ cb 26 /: 8c 8c 0b 0 / } ac 3f * cc 0b 0 / } 8d 8d 32 / / / / / ? ad 4e / cd 32 / / / / / ? 8e 8e 31 . / > ae 4b . / del ce 31 . / > 8f 8f 3a up arrow af 3a up arrow cf 3c pgup 90 90 3b down arrow b0 3b down arrow d0 3d pgdn 91 91 37 left arrow b1 37 left arrow d1 39 end 92 91 3e right arrow b2 3e right arrow d2 38 home 93 91 63 scrl lock b3 63 scrl lock d3 62 numlk 94 91 35 ins b4 35 ins d4 64 prtscr 95 91 36 delr b5 36 delr d5 7e sysreq 96-af 92-af 0 null b6-cf 0 null d6-ef 0 null
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-13 programming the keyboard matrix the keyboard matrix is a contiguous section of ACPITROLLER ? memory divided into four subsections. you program the keyboard matrix by downloading the desired values into the matrix memory. you do this with the four download commands, ba, bb, bc, and bd, which are part of the hidc usar expanded command set. chapter 2, the hid controller interface chapter, explains the role of each command and how to issue it. the first of the four sections of the keyboard matrix is 128 bytes long. it maps the row and column coordinates generated by a keyboard into usar numbers, described above. the section is organized as follows: byte offset function 0 usar number for row 0, column 0 1 usar number for row 1, column 0 2 usar number for row 2, column 0 3 usar number for row 3, column 0 4 usar number for row 4, column 0 5 usar number for row 5, column 0 6 usar number for row 6, column 0 7 usar number for row 7, column 0 8 usar number for row 0, column 1 . . . . . . 124 usar number for row 4, column 15 125 usar number for row 5, column 15 126 usar number for row 6, column 15 127 usar number for row 7, column 15 usar numbers 0-7fh correspond to the standard ps/2 key numbers and are used for keys that are unaffected by the numeric lock and function keys. key numbers 80h to 9fh are reserved for those keys that are influenced by the numeric lock and function keys. row and column coordinates that are assigned these numbers then generate a second code lookup from one of sections 2, 3, or 4.
ACPITROLLER ? basic ur8hc342 preliminary system management controller product alphakey ? keyboard manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 3-14 each of the remaining three sections of the keyboard matrix is 32 bytes long and contains the usar number generated by a keypress in one of three states: 1. no control keys selected 2. numeric lock selected 3. function selected for example, on the fujitsu 7654 keyboard, key j is at row 7, column 8 and is a part of the integrated numeric keypad (number 2). when the keyboard is in numeric lock, the j key generates the keycode for keypad 2. so, at offset 47h of matrix section one (which corresponds to row 7, column 8), we assign the value 8ah, which is one of the reserved usar numbers. matrix section two contains the keycode to be generated when no control keys are pressed, and the offset into this table is calculated by subtracting 128 from the value we put into matrix section one. therefore, the offset into matrix section two is 10, which is where we put the value 23h, which is the standard keycode generated by the j key. if numeric lock was selected, then the offset is used to lookup in matrix section three, which would contain the keycode 41h, which is numeric 2. if function was selected, then the offset is used to lookup in matrix section four, which would contain 23h, since the j key is not affected by the function key. the four sections comprise page 0 of the matrix ram. matrix section one is at offset 0, section two is at offset 80h, section three is at offset a0h, and section four is at offset c0h.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company doc8-342-tr-080 confidential 4-1 ? 1999-2000 usar ? a semtech company usar ur8hc342 ACPITROLLER? basic alphamouse? pointing devices manager overview in legacy mode, the ur8hc342 usar alphamouse? pointing devices manager can simultaneously support up to three standard mice connected to both the external and internal ps/2 ports of the ACPITROLLER?. the usar alphamouse? handles ps/2 mouse commands, supports external mouse hot-plug-ins, and merges internal and external mouse data. in multiplexing mode, operating with a multiplexing host driver, ur8hc342 usar alphamouse? pointing devices manager can simultaneously support up to three pointing devices connected to both the external and internal ps/2 ports of the ACPITROLLER?. these pointing devices can include proprietary and non-standard devices, depending on the driver(s). the usar alphamouse? does not merge the data, but keeps data reports from separate pointing devices separate for handling by the multiplexing host driver. features at a glance ? alphamouse? pointing device manager supports hot-plugging and hot- swapping of standard two-button and three-button mice without a special driver; it also supports hot-plugging and hot-swapping of mousewheel mice with a mousewheel-capable driver ? two external ps/2 ports for external keyboard and mouse with auto-detect and hot-plug support ? simultaneous operation of external and internal pointing devices, merging internal and external mouse data ? support of mousewheel functionality for both embedded and external pointing devices, even with hot-plug connections, with a mousewheel- capable driver ? operates safely with ps/2 mouse protocol ? alphamouse? performs active ps/2 multiplexing of input from different types of mice simultaneously, with the appropriate driver(s) ? support of the usar screencoder? ps/2 absolute and relative touchscreen encoder, with the appropriate driver ? support of the five-button mouse, with an appropriate driver
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 4-2 multiplex mode a host driver that supports active ps/2 multiplexing sends a special sequence of commands to the usar ur8hc342 ACPITROLLER? as follows: the host writes 0xd3 to output port 0x64 the host writes 0xf0 to output port 0x60 the controller responds with 0xf0 on input port 0x60 the host writes 0xd3 to output port 0x64 the host writes 0x56 to output port 0x60 the controller responds with 0x56 on input port 0x60 the host writes 0xd3 to output port 0x64 the host writes 0xa4 to output port 0x60 the controller responds with 0x11 on input port 0x60 by responding to last part of the sequence with 0x11 instead of 0xa4, the ACPITROLLER? shows that it supports active ps/2 multiplexing standard, version 1.1. at this point, the ACPITROLLER? alphamouse enters multiplex mode. while in multiplex mode, the ACPITROLLER? alphamouse behaves as follows: when it receives a data report from a pointing device on a ps/2 port, it adds a prefix to the data report indicating which ps/2 port, and passes the report with the prefix to the multiplexing driver. when it receives a command from the multiplexing driver, it strips the prefix from the command, and sends the command to the ps/2 port indicated by the prefix.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company doc8-342-tr-080 confidential 4-3 ? 1999-2000 usar ? a semtech company legacy mode functional description and handling of ps/2 ports the usar alphamouse? pointing devices manager receives its pointing device input through one or more of the usar ACPITROLLER? basic ps/2 ports. the usar alphamouse? can handle up to three pointing devices. the ps/2 ports driver auto-detects the type of device connected to each ps/2 port. if the device reports itself as a pointing device, ps/2 ports driver connects it to the usar alphamouse? pointing devices manager for proper initialization and further data and command handling. the usar alphamouse? pointing devices manager communicates with the host system through the mouse port of the hid controller. ? usar alphamouse? block diagram ps/2 ports driver ps/2 port0 ps/2 port1 ps/2 port2 alphamouse? pointing devices manager hid controller
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 4-4 local handling mode in legacy mode, the usar alphamouse? supports two distinct modes of pointing devices operation; the ?local handling? and the ?system handling? modes. in the ?local handling? mode, the usar alphamouse? responds locally to every command issued by the driver, including configuration commands for mousewheel support. the alphamouse? initializes up to three ps/2 pointing devices and handles all configuration and data transactions individually. if an intellimouse? device is hot-plugged in, it is configured by the usar alphamouse? to enable mousewheel data reporting. x, y and z data reported by all the connected pointing devices is both accumulated and reported to the host driver as if they originated from a single ps/2 device. this default mode of operation supports all known ps/2 pointing devices, providing the least system intervention and the maximum flexibility in the usage of external ps/2 devices with the usar ACPITROLLER? basic. the following drawing illustrates a possible configuration that can be supported by the usar alphamouse? pointing devices manager.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company doc8-342-tr-080 confidential 4-5 ? 1999-2000 usar ? a semtech company usar alphamouse? sample user model in this example, a pointing device is connected to each of the three alphamouse? ps/2 ports, one internal and two external a usar pixipoint? force-stick type of embedded mouse, emulating a three-button mouse, is connected to the internal ps/2 port. a two-button touchpad is connected to one of the external ps/2 ports and a microsoft ? intellimouse ? to the other. in our example, we assume that the laptop is loaded with windows 98 and the microsoft ? intellimouse ? driver. in this configuration, the usar ACPITROLLER? basic will operate as described below. ps/2 ports driver alphamouse? pointing device manager hid controller embedded 3 button pixipoint? force stick pointer 2 button touchpad ms intellimouse compatible mouse
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 4-6 ? the ps/2 ports driver detects the presence of each pointing device and notifies the pointing device manager of their presence. ? the system mouse driver interrogates the ACPITROLLER? basic about its capabilities. the usar alphamouse? detects the mousewheel initialization sequence issued by the driver and reports it to the system driver as an intellimouse? compatible mouse, thus changing its report scheme from 3 to 4 bytes. ? the usar alphamouse? pointing device manager interrogates each connected pointing device about its capabilities. the alphamouse? initializes the microsoft intellimouse? to report mousewheel data. ? the usar alphamouse? collects x, y and z (where available) data and composes a single report to present to the driver. the pixipoint? and the touchpad report only x and y coordinates. ? any change in the configuration, such as the hot-plug-in of another pointing device, is handled internally by the usar alphamouse? and the transaction details are hidden from the driver.
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company doc8-342-tr-080 confidential 4-7 ? 1999-2000 usar ? a semtech company ps/2 mouse commands the usar alphamouse? internally handles all ps/2 mouse commands. these commands, as well as the responses to them, are listed in the following table. usar alphamouse? ps/2 commands command response description ffh fah, aah, 00h mouse reset command feh xxh resends last package f7h ? fdh feh invalid f6h fah set default f5h fah disable f4h fah enable f3h , xxh fah, fah sampling rate f2h fah, 00h read device id f1h feh invalid command f0h fah set remote mode efh feh invalid command eeh fah set wrap mode edh feh invalid command ech fah reset wrap mode ebh fah, xxh, xxh, xxh, read data eah fah set stream mode e9h fah, xxh, xxh, xxh status request e8h, 0xh fah, fah set resolution e7h fah set scaling 2:1 e6h fah reset scaling 1:1
ACPITROLLER? basic ur8hc342 preliminary system management controller product alphamouse? pointing devices manager usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 4-8 external mouse hot-plug support the usar alphamouse? pointing devices manager supports the hot-plug in of external mice. the pointing devices manager initializes and configures each connected device dynamically, according to the system mouse driver settings. the usar alphamouse? pointing devices manager auto-detects three-button mice, as well as mousewheel type of devices, and enables every feature that the system driver supports. transparent mousewheel support the usar alphamouse? supports mousewheel reporting. the usar alphamouse? pointing device manager generates a special initial sequence to the host in order to alert the driver to utilize the mousewheel report format. the mousewheel has a different report packet than a standard ps/2 mouse. as a result, the two cannot be integrated. the usar alphamouse? pointing device manager monitors the connected mice. if the system mouse driver is initialized to work in mousewheel mode, the usar alphamouse? alters its reports to correspond to the mousewheel format. in this manner, both the internal and external mice data can be integrated.
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-1 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company usar ur8hc342 ACPITROLLER? embedded controller interface ur8hc342 ec bus interface the usar ur8hc342 acpi embedded controller (ec) interfaces to the host isa bus via two i/o addresses. the following diagram illustrates the embedded controller architecture that includes a dedicated acpi interface. notes: ur_add represents the decoded base address for the ur8hc342 embedded controller isa ports. default value is 0x62. ec data input register (ur_add) ec data output register (ur_add) ec status/command register (ur_add+4) sci interface and main firmware and smbus interface smbus host interface and internal simulation smbus devices isa data read status read command write sci interrupt swi interrupt system suspend power button power button override lid
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-2 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company ur8hc342 embedded controller registers the usar ur8hc342 smbus ec contains three registers that occupy two i/o locations. the registers are listed in the following table. usar ur8hc342 registers name description i/o function i/o port address ec_sc (r ) status ior ur_add+4 ec_sc (w) command iow ur_add+4 ec_data data ior/iow ur_add ec status register, ec_sc (r) ec_sc (r) is a read-only register that indicates the current status of the embedded controller interface. it contains the following fields. ec_sc (r) ec status register bit definitions bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ign smi_evt sci_evt burst cmd ign ibf obf ec_sc (r) ec status register bit definitions ign ignored smi_evt smi event 1 ? indicates smi event is pending (requesting smi query) 0 ? indicates no smi event pending sci_evt sci event 1 ? indicates sci event is pending (requesting sci query) 0 ? indicates no sci events are pending burst burst mode 1 ? controller is in burst mode for polled command processing 0 ? controller is in normal mode for interrupt-driven command processing cmd command/data 1 ? byte in data register is a command byte (only set by host, used by ec) 0 ? byte in data register is a data byte (only clear by host, used by ec) ibf input buffer full 1 ? input buffer is full (data ready for ec) 0 ? input buffer is empty, generate sci interrupt obf output buffer full 1 ? output buffer is full (data ready for host), generate sci interrupt 0 ? output buffer is empty
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-3 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company command register, ec_sc (w) ec_sc (w) is a write-only register that allows commands to be issued to the embedded controller. writes to this register are latched in the input data register and the input buffer full (ibf) flag is set in the status register. writes to this location also cause the command bit to be set in the status register. this enables the embedded controller to differentiate the start of a command sequence from a data byte write operation. data register, ec_data(r/w) ec_data(r/w) is a read/write register that allows both command/data bytes to be issued to the embedded controller and the os to read data returned by the embedded controller. writes to this port by the host are latched into the input data register and the input buffer full (ibf) flag is set in the status register. reads from this register return data from the output data register and clear the output buffer full (obf) flag in the status register.
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-4 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company port operation the following diagrams illustrate the sequence for issuing commands and data to the ec through the host interface. send command byte the host can issue a command byte to command register directly. ibf = 0 ? yes write command byte to command port ur_add+4; no end
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-5 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company send data byte the host can send a data byte to the data port directly. ibf = 0 ? yes write data byte to data port ur_add; no end
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-6 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company ec commands the operating system can communicate with the ec using the standard acpi embedded controller command set. these commands are listed and detailed below. usar ur8hc342 acpi controller command set embedded controller command command byte encoding read embedded controller (rd_ec) 0x80 write embedded controller (wr_ec) 0x81 burst enable embedded controller (be_ec) 0x82 burst disable embedded controller (bd_ec) 0x83 query embedded controller (qr_ec) 0x84 read embedded controller, rd_ec (0x80) the rd_ec (0x80) command allows the os to read a byte in the address space of the embedded controller. the exact command sequence is detailed below. this command is reserved exclusively for use by the os and proceeds based on interrupts from the ec. the values of the ibf and obf flags determine the interrupt generation as follows. rd_ec (0x80) command sequence step action register port address sci interrupt 1 send command header command port ur_add+4 interrupt on ibf=0, command header has been read 2 send address to be read data ur_add no interrupt 3 host read data data ur_add interrupt on obf=1, data is available
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-7 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company write embedded controller, wr_ec (0x81) the wr_ec (0x81) command byte allows the os to write a byte in the address space of the embedded controller. this command byte is reserved exclusively for use by the os and proceeds based on interrupts from the ec. the value of the ibf flag determines the interrupt generation as follows. wr_ec (0x81) command sequence step action register port address sci interrupt 1 send command header command port ur_add+4 interrupt on ibf=0, command header has been read 2 send address to be written data ur_add interrupt on ibf=0, address has been read 3 host write data data ur_add interrupt on ibf=0, data has been read burst enable embedded controller, be_ec (0x82) the be_ec (0x82) command allows the os to request dedicated attention from the ec and, except for critical events, the ec from doing tasks other than receiving command and data from the os. this command is an optimization that allows the host processor to issue several commands back-to-back, in order to reduce latency at the embedded controller interface. when the controller is in the burst mode, it should transition to the burst disable state if the host does not issue a command within the following guidelines: ? first access 400 microseconds ? subsequent accesses 50 microseconds each ? total burst time 1 millisecond if the ec disables burst mode for any reason other than the burst disable command, it generates an sci to the os to indicate the change. while in burst mode, the embedded controller follows these guidelines for the os driver: ? scis are generated as normal, including ibf=0 and obf=1. ? accesses should be responded to within 50 microseconds.
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-8 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company following is the burst enable command sequence. be_ec (0x82) command sequence step action register port address sci interrupt 1 send command header command port ur_add+4 no interrupt 2 host read burst ack byte data ur_add interrupt on obf=1, data is available burst disable embedded controller, bd_ec (0x83) this command releases the embedded controller from a previous burst enable command and allows it to resume normal processing. the os sends this command after it has completed its entire queued command sequence to the embedded controller. following is the burst disable command sequences. bd_ec (0x83) command sequence step action register port address sci interrupt 1 send command header command port ur_add+4 interrupt on ibf=0, command header has been read query embedded controller, qr_ec (0x84) the os driver sends the qr_ec (0x84) command when the sci_evt flag in the ec_sc register is set. when the ec has detected a system event that must be communicated to the os, it first sets the sci_evt flag in the ec_sc register, generates an sci, and then waits for the os to send the query (qr_ec) command. the os detects the embedded controller sci, sees the sci_evt flag set, and sends the query command to the embedded controller. upon receipt of the qr_ec command byte, the ec places a notification byte with a value between 0-255, indicating the cause of the notification. the notification byte indicates which interrupt handler operation the os should execute in order to process the embedded controller sci. the query value of zero is reserved for a spurious query result and indicates ?no outstanding event.?
ACPITROLLER? basic ur8hc342 preliminary system management controller product embedded controller interface usar ? a semtech company 5-9 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company following is the query ec command sequences. qr_ec (0x84) command sequence step action register port address sci interrupt 1 send command header command port ur_add+4 no interrupt 2 host read query value data ur_add interrupt on obf=1, data is available smbus host controller notification header (optional), os_smb_evt the os_smb_evt query command notification header is the special return code that indicates events from an smbus controller implemented within an embedded controller. these events include the following. os_smb_evt events num notification event description 1 00h no outstanding event 2 01h command complete response to os smbus command 3 02h command error response to os smbus command 4 03h alarm alarm from smbus device the actual notification value is declared in the smbus host controller device object in the acpi name space. for more details on the smbus host functioning in the acpi system, refer to the smbus host controller interface section of this specification.
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ACPITROLLER? basic ur8hc342 preliminary system management controller product sci & swi interrupt generation usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 6-1 usar ur8hc342 ACPITROLLER? sci & swi interrupt generation event interrupts the usar ur8hc342 ACPITROLLER? generates two types of interrupts, the sci and the swi. the type of interrupt generated depends on the type of event that caused it. when a standard smbus event occurs, the ec generates an sci interrupt. for any other general purpose events (gpe), an swi interrupt occurs. such events may include lid events, dock events, or power button presses. swi interrupts have the ability to wake up the system if it is in suspend. sci interrupts do not do this. below is a diagram describing the generation of these two interrupts. generation of sci and swi event interrupts x ecscien.x sci interrupt x ecswien.x swi interrupt event status x standard smbus event gpe
ACPITROLLER? basic ur8hc342 preliminary system management controller product sci & swi interrupt generation usar ? a semtech company 6-2 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company swi sources there are a number of events that trigger an swi interrupt: up to eight external events can trigger a swi interrupt; in addition, the usar ur8hc342 internally generates an swi in response to certain smbus conditions. eight pins, labeled gpe0 ? gpe7, can be connected to event sources to generate swi interrupts. each of these pins has specific traits, making some more suitable than others for certain functions. pins gpe0 and gpe1 are able to generate gp events on detection of positive- or negative-edge signals. this makes them most suitable for handling occasional events like docking insertion/removal, and lid open/close, where processing is required only when a change in input is detected. gpe2 to gpe7 trigger on logical low signal level, rather than signal edge. this makes them more suitable for functions like power button override, which requires the power button to be held down for four seconds. gpe4 and gpe7 have no internal pullup resistors and require external pullup to be used. gpe3-6 can enable internal pullup only when smbus2 is disabled. in order to use these pins as gpe input pins, the user must enable them as gpe pins in the gpecfg register. if these pins are not used as gpe pins, they are available as general i/o pins. in addition to these externally generated gpe events, the usar ur8hc342 generates a swi interrupt in response to certain smbus conditions. the ec monitors the smbus status. if the smbus becomes stuck, the ec can generate a swi to the system to report this. if a generic i 2 c device (not identified as a smart battery, charger, or selector) generates an alert, the ec can generate an swi interrupt. in addition, under certain conditions, battery alarms and selector and charger alerts can generate swi interrupts, as described below.
ACPITROLLER? basic ur8hc342 preliminary system management controller product sci & swi interrupt generation usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 6-3 special smbus events one of the differences between sci and swi events is that an swi interrupt can wake up a host in suspend mode, while an sci interrupt cannot. as described previously, standard smbus events generate sci interrupts. an sci interrupt does not wake up the system if it is in suspend mode. some smbus events, however, may occur when the system is in suspend, and need to wake up the system. these events are battery alarm and selector and charger alert. for these events, if the system is in suspend, the ur8hc342 first simulates a power button press. this power button press generates an swi interrupt, which wakes up the system. once the system is active again, the regular sci interrupt can be generated to indicate the smbus event.
ACPITROLLER? basic ur8hc342 preliminary system management controller product sci & swi interrupt generation usar ? a semtech company 6-4 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company interrupt generation the ec interrupt model uses pulsed interrupts to speed the clearing process. the sci interrupts are firmware-generated, using ec general- purpose outputs, and have the waveform shown in the figure below. figure 13-3. the os treats these interrupts as edge events. ec interrupt process waveform 10us interrupt detected interrupt serviced and cleared
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-1 usar ur8hc342 ACPITROLLER? smbus host controller interface overview this chapter describes the system management bus (smbus) host controller interface. the smbus address space is a generic address space defined in the acpi specification. following is a description of the usar ur8hc342 ACPITROLLER? implementation of the smbus host controller within the embedded controller. this implementation allows the os directly to address devices on the smbus. smbus overview the smbus is a two-wire interface based on i2c protocol. a low-speed bus, it provides multi-device addressing as well as bus arbitration. for more information on the smbus generally, refer to the complete set of smbus specifications published by the smart battery system implementers forum (sbs-if) at http://www.sbs-forum.org/. the smbus host controller interface the smbus host controller interface allows the host processor, under control of the os, to manage devices on the smbus. among typical devices that reside on the smbus are smart batteries, smart chargers, contrast/backlight control, and temperature sensors. due to the sensitive nature of some of these devices, the smbus host controller is required to monitor and filter certain smbus commands addressed to the smart battery system. this particular function of the ec is essential for the system?s safety, since it prevents errant applications or viruses from creating system hazards through improper control of the battery subsystem. the smbus host controller interface provides a method of communicating with smbus devices through a block of registers that reside in the embedded controller space. in addition, the smbus host controller handles certain smbus functions related to alerts and error conditions. the usar ur8hc342 ACPITROLLER? supports the standard set of registers defined in the acpi specification that an acpi-compatible os can use to communicate with smbus devices. the following sections detail the smbus host controller functionality, the register interface, and configuration parameters.
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-2 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company smbus alarm message & smbus alert process in an smbus system, several devices can be programmed to notify the host system when specific events occur. a smart battery, for example, issues an alarm message to signal a critical capacity condition. other smbus devices, including smart selectors and smart chargers, issue alerts to inform the smbus host controller of an internal status change. smbus devices typically notify the smbus host controller that such an event has occurred by asserting the smbus alert signal. when the usar ur8hc342 ACPITROLLER? smbus host controller detects that the smbus alert signal has been asserted, it first checks the chgqren and slctqren bits in r0 (ec configuration register 0) in order to determine whether to query for a smart charger- or a smart selector- generated alert. if either one of these bits is set, the smbus host controller queries the appropriate device and checks its status. the status is then anded with the appropriate masks and, if the result is nonzero, the appropriate device status message is placed into the ec smbus alarm buffer and an sci is generated. the address used to query the selector and charger depends on the system configuration. if the system includes a selector and a charger at different addresses, the queries are made to the addresses specified. if the system includes a selector and charger device residing at the same address, the query is to that specific address. this configuration controlled by the chgslct bit in r0. if the alert did not come from one of these two devices, the alert is considered to come from a generic i 2 c device. the alert can generate an swi interrupt, not an sci interrupt. the smbus host generates an swi interrupt if the deviceen flag in ec_swien is set. if querying for the selector is disabled (slctqren is clear), alerts from the selector are treated the same as for any other i 2 c devices. similarly, if querying for the charger is disabled (chgqren is clear), alerts from the charger are treated in the same manner as any other i 2 c device. in addition to smbus devices generating alerts, the smart battery can generate an alarm to indicate a critical condition. when the usar ur8hc342 ACPITROLLER? receives a smart battery alarm, it retrieves the alarm message and ands it with the contents of r14 (the ec battery alarm mask register). if the result is nonzero, the ec puts an alarm message into the ec smbus alarm buffer and generates an sci interrupt to the system. note that once an alarm message has been received, the smbus host controller does not receive additional alarm messages until the alrm status bit is cleared.
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-3 smbus error recovery the usar ur8hc342 ACPITROLLER? monitors the smbus. if it detects that the smbus has gotten stuck, the ec tries to recover the bus. if it fails and the smbus stuck event is enabled (by setting stucken in register r05), the ec issues an swi interrupt to the system. smbus host register space the smbus host interface is a flat array of registers that are arranged in a block of system address space. the smbus register space base address (smb_base) corresponds to zero (0) in the usar ur8hc342?s address space. smbus host registers the table below lists the registers defined for the smbus host with their reset values. each register is eight bits wide. the first group of registers contains the standard smbus host registers, as listed in the acpi specification section on embedded controllers. a list of these registers follows. an appendix to this document provides brief descriptions of these registers. full descriptions are given in the acpi specification. the method of initiating the different protocols on the smbus through these registers is also briefly described in the appendix, and fully provided in the acpi specification.
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-4 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company standard smbus host registers location register name reset default description smb_base+0 smb_prtcl 00000000 protocol register smb_base+1 smb_sts 00000000 status register smb_base+2 smb_addr 00000000 address register smb_base+3 smb_cmd 00000000 command register smb_base+4 smb_data[0] 00000000 data register zero smb_base+5 smb_data[1] 00000000 data register one smb_base+6 smb_data[2] 00000000 data register two smb_base+7 smb_data[3] 00000000 data register three smb_base+8 smb_data[4] 00000000 data register four smb_base+9 smb_data[5] 00000000 data register five smb_base+10 smb_data[6] 00000000 data register six smb_base+11 smb_data[7] 00000000 data register seven smb_base+12 smb_data[8] 00000000 data register eight smb_base+13 smb_data[9] 00000000 data register nine smb_base+14 smb_data[10] 00000000 data register ten smb_base+15 smb_data[11] 00000000 data register eleven smb_base+16 smb_data[12] 00000000 data register twelve smb_base+17 smb_data[13] 00000000 data register thirteen smb_base+18 smb_data[14] 00000000 data register fourteen smb_base+19 smb_data[15] 00000000 data register fifteen smb_base+20 smb_data[16] 00000000 data register sixteen smb_base+21 smb_data[17] 00000000 data register seventeen smb_base+22 smb_data[18] 00000000 data register eighteen smb_base+23 smb_data[19] 00000000 data register nineteen smb_base+24 smb_data[20] 00000000 data register twenty smb_base+25 smb_data[21] 00000000 data register twenty-one smb_base+26 smb_data[22] 00000000 data register twenty-two smb_base+27 smb_data[23] 00000000 data register twenty-three smb_base+28 smb_data[24] 00000000 data register twenty-four smb_base+29 smb_data[25] 00000000 data register twenty-five smb_base+30 smb_data[26] 00000000 data register twenty-six smb_base+31 smb_data[27] 00000000 data register twenty-seven smb_base+32 smb_data[28] 00000000 data register twenty-eight smb_base+33 smb_data[29] 00000000 data register twenty-nine smb_base+34 smb_data[30] 00000000 data register thirty smb_base+35 smb_data[31] 00000000 data register thirty-one smb_base+36 smb_bcnt 00000000 block count register smb_base+37 smb_alrm_addr 00000000 alarm address smb_base+38 smb_alrm_data[0] 00000000 alarm data register zero smb_base+39 smb_alrm_data[1] 00000000 alarm data register one
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-5 the second group of registers contains registers that are usar-defined smbus host registers. these allow the user to access and configure all of the added features available on the ur8hc342, such as sbs device events and interrupt generation. usar-defined smbus host registers ec offset register no. register name read / write power-up / reset default value 40 r00 ec configuration register 0 r/w 00h 41 r01 ec configuration register 1 r/w 00h 42 r02 ec configuration register 2 r/w 00h 43 r03 ec configuration register 3 r/w 00h 44 r04 ec swi gpe enable register 0 r/w 00h 45 r05 ec swi gpe enable register 1 r/w 00h 46 r06 ec swi gpe status register 0 r/w 00h 47 r07 ec swi gpe status register 1 r/w 00h 48 r08 ec selector alarm high mask register 0 r/w 00h 49 r09 ec selector alarm high mask register 1 r/w 00h 50 r10 ec selector alarm low mask register 0 r/w 00h 51 r11 ec selector alarm low mask register 1 r/w 00h 52 r12 ec charger alarm high mask register r/w 00h 53 r13 ec charger alarm low mask register r/w 00h 54 r14 ec battery alarm mask register r/w 00h 55 r15 8042 configuration register 0 r 00h 56 r16 8042 configuration register 1 r 00h 57 r17 8042 configuration register 2 r 00h 58 r18 reserved 59 r19 gio0 data/direction register r/w 00h 60 r20-r40 reserved 81 r41 gio1 mode register r/w 00h 82 r42 gio1 data/direction register r/w 00h 83 r43 gio1 pwm1 high byte register r/w 00h 84 r44 gio1 pwm1 low byte register r/w 00h 85 r45 gio1 pwm0 high byte register r/w 00h 86 r46 gio1 pwm0 low byte register r/w 00h 87 r47 gio1 da1 data register r/w 00h 88 r48 gio1 da0 data register r/w 00h 89 r49 gio2 data/direction register r/w 00h 90 r50 gio2 ad2 data high byte register r 00h 91 r51 gio2 ad2 data low byte register r 00h 92 r52 gio2 ad1 data high byte register r 00h 93 r53 gio2 ad1 data low byte register r 00h 94 r54 gio2 ad0 data high byte register r 00h 95 r55 gio2 ad0 data low byte register r 00h 96 r56 gio3 direction register r/w 00h 97 r57 gio3 data register r/w 00h
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-6 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company r00: ec configuration register 0 this register contains the control bytes that determine the ec and smbus work modes. r00: ec configuration register 0 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res res res res res chgqren slctqren chgslct r00: ec configuration register 0 bit descriptions res reserved chgqren charger alert query enable this setting controls whether the smbus host queries the charger upon receiving an alert. 1? enable 0 ? disabled slctqre selector alert query enable this setting controls whether the smbus host queries the selector upon receiving an alert 1 ? enable 0 ? disabled chgslct selector and charger combined device this selects what configuration is used. in some systems, the charger and the selector are different devices at different addresses, while in some systems, the selector and charger are combined into one device at one address 1 ? separate address 0 ? combined device at same address
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-7 r01: ec configuration register 1 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 kkleden clleden nlleden slleden res res res res r01: ec configuration register 1 bit descriptions res reserved slleden enable gio03 as scroll lock led 1? enable as scroll lock led 0 ? general purpose i/o nlleden enable gio02 as numeric lock led 1? enable as numeric lock led 0 ? general purpose i/o clleden enable gio01 as caps lock led 1? enable as caps lock led 0 ? general purpose i/o kkleden enable gio00 as katakana led 1? enable as katakana led 0 ? general purpose i/o
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-8 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company r02: ec configuration register this register controls which of the available general purpose event (gpe) pins are selected to function as gpe inputs and which remain general- purpose i/o (gp i/o) pins. setting a bit in the register to 1 configures the corresponding pin for gpe input, and resetting it to 0 configures it to be used for gp i/o. note that a separate register, r04, determines whether a given gpe pin is enabled r02: ec configuration register 2 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpe7as gpe6as gpe5as gpe4as gpe3as gpe2as gpe1as gpe0as r02: ec configuration register 2 bit descriptions gpe7as assign pin gpe7 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe6as assign pin gpe6 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe5as assign pin gpe5 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe4as assign pin gpe4 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe3as assign pin gpe3 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe2as assign pin gpe2 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe1as assign pin gpe1 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other gpe0as assign pin gpe0 to an swi general purpose event (gpe) 1? assign pin to an swi general purpose event (gpe) 0 ? assign pin to general purpose i/o (gpio) or other
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-9 r03: ec configuration register 3 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpe7edge gpe6edge res res res pwbover res res r03: ec configuration register 3 bit descriptions res reserved gpe7edge make general purpose event gpe7 rising edge sensitive 1? make general purpose event gpe7 rising edge sensitive gpe6edge make general purpose event gpe6 rising edge sensitive 1? make general purpose event gpe6 rising edge sensitive pwbover enable power button override 1? enable power button override r04: ec swi gpe enable register 0 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpe7en gpe6en gpe5en gpe4en gpe3en gpe2en gpe1en gpe0en r04: ec swi gpe enable register 0 bit descriptions gpe7en enable swi general purpose event gpe7 1? enable swi general purpose event gpe7 gpe6en enable swi general purpose event gpe6 1? enable swi general purpose event gpe6 gpe5en enable swi general purpose event gpe5 1? enable swi general purpose event gpe5 gpe4en enable swi general purpose event gpe4 1? enable swi general purpose event gpe4 gpe3en enable swi general purpose event gpe3 1? enable swi general purpose event gpe3 gpe2en enable swi general purpose event gpe2 1? enable swi general purpose event gpe2 gpe1en enable swi general purpose event gpe1 1? enable swi general purpose event gpe1 gpe0en enable swi general purpose event gpe0 1? enable swi general purpose event gpe0
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-10 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company r05: ec swi gpe enable register 1 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res mousen kybden stucken alrten slcten chrgen batten r05: ec swi gpe enable register 1 bit descriptions res reserved mousen enable mouse wakeup swi general purpose event (gpe) 1? enable mouse wakeup swi general purpose event (gpe) kybden enable keyboard wakeup swi general purpose event (gpe) 1? enable keyboard wakeup swi general purpose event (gpe) stucken enable smbus stuck error swi general purpose event (gpe) 1? enable smbus stuck error swi general purpose event (gpe) alrten enable smbus alert swi general purpose event (gpe) 1? enable smbus alert swi general purpose event (gpe) slcten enable selector alarm swi general purpose event (gpe) 1? enable selector alarm swi general purpose event (gpe) chrgen enable charger alarm swi general purpose event (gpe) 1? enable charger alarm swi general purpose event (gpe) batten enable battery alarm swi general purpose event (gpe) 1? enable battery alarm swi general purpose event (gpe)
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-11 r06 and r07: ec swi gpe status registers these registers contain the ec swi interrupt events status bits, which correspond to the events controlled by the ec swi gpe enable registers (r04 and r05). for each bit controlling an swi event in an enable register, the same position bit in the corresponding status register indicates the status of that event. each status bit is set by the swi event and can be cleared only by the host writing 1 to its bit position. the status bits are set and reset regardless of whether each event is enabled. enabling an event controls only whether an interrupt is generated on the event. r06: ec swi gpe status register 0 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpe7st gpe6stn gpe5st gpe4st gpe3st gpe2st gpe1st gpe0st r06: ec swi gpe status register 0 bit descriptions gpe7st flag swi general purpose event gpe7 1? flag swi general purpose event gpe7 gpe6st flag swi general purpose event gpe6 1? flag swi general purpose event gpe6 gpe5st flag swi general purpose event gpe5 1? flag swi general purpose event gpe5 gpe4st flag swi general purpose event gpe4 1? flag swi general purpose event gpe4 gpe3st flag swi general purpose event gpe3 1? flag swi general purpose event gpe3 gpe2st flag swi general purpose event gpe2 1? flag swi general purpose event gpe2 gpe1st flag swi general purpose event gpe2 1? flag swi general purpose event gpe2 gpe0st flag swi general purpose event gpe1 1? flag swi general purpose event gpe1
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-12 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company r07: ec swi gpe status register 1 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res mousst kybdst stuckst alrtst slctst chrgst battst r07: ec swi gpe status register 1 bit descriptions res reserved mousst flag mouse wakeup swi general purpose event (gpe) 1? flag mouse wakeup swi general purpose event (gpe) kybdst flag keyboard wakeup swi general purpose event (gpe) 1? flag keyboard wakeup swi general purpose event (gpe) stuckst flag smbus stuck error swi general purpose event (gpe) 1? flag smbus stuck error swi general purpose event (gpe) alrtst flag smbus alert swi general purpose event (gpe) 1? flag smbus alert swi general purpose event (gpe) slctst flag selector alarm swi general purpose event (gpe) 1? flag selector alarm swi general purpose event (gpe) chrgst flag charger alarm swi general purpose event (gpe) 1? flag charger alarm swi general purpose event (gpe) battst flag battery alarm swi general purpose event (gpe) 1? flag battery alarm swi general purpose event (gpe)
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-13 r08-r11: ec selector alarm mask registers ? r08: ec selector alarm high mask register 0 ? r09: ec selector alarm high mask register 1 ? r10: ec selector alarm low mask register 0 ? r11: ec selector alarm low mask register 1 these registers contain the smart selector alert message mask. this controls whether an alert from the smart selector generates an sci interrupt. when the smart selector sends an smbus alert, if the selector is enabled the smbus host queries the selector state. each bit of the state is masked with the corresponding selector alarm mask flag, and if the result is nonzero, an sci interrupt is generated. the high mask registers (r08 and r09) control whether a high level for a given bit of the selector state generates an interrupt, while the low mask registers (r10 and r11) control whether a low level for a given bit of the selector state generates an interrupt. by using both of these register pairs, the user can generate an interrupt on either low or high level ? or both ? for each of the selector state bits.
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-14 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company r08 / r10 ec selector alarm high / low mask register 0 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 batdchg batcchg batbchg batachg batdpres batcpres batbpres batapres r08 / r10 ec selector alarm high / low mask register 0 bit descriptions batdchg mask for battery d connected to charger state batcchg mask for battery c connected to charger state batbchg mask for battery b connected to charger state batachg mask for battery a connected to charger state batdpres mask for battery d present state batcpres mask for battery c present state batbpres mask for battery b present state batapres mask for battery a present state r09/ r11 ec selector alarm high / low mask register 1 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 batdsmb batcsmb batbsmb batasmb batdpwr batcpwr batbpwr batapwr r09/ r11 ec selector alarm high / low mask register 1 bit descriptions batdsmb mask for battery d connected to smbus state batcsmb mask for battery c connected to smbus state batbsmb mask for battery b connected to smbus state batasmb mask for battery a connected to smbus state batdpwr mask for battery d powering state batcpwr mask for battery c powering state batbpwr mask for battery b powering state batapwr mask for battery a powering state
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-15 r12 and r13: ec charger alarm mask registers ? r12: ec charger alarm high mask register ? r13: ec charger alarm low mask register these registers contain the smart charger alert message masks, which use the same mechanism as the smart selector alarm message masks. when the smart charger sends an smbus alert, if the charger is enabled the smbus host queries the charger status. each bit of its status is masked with the corresponding flag in these registers, and if the result is nonzero, an sci interrupt is generated. r12 controls whether a high level for a given bit of the charger status generates an interrupt, while r13 controls whether a low level for a given bit of the charger status generates an interrupt. by using both of these register sets, the user can generate an interrupt on either low-or high-level ? or both ? for each of the charger status bits. the register contains the following fields. r12 / r13 ec charger alarm high / low mask register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ac_pres bat_pres pwrfail alrminh thrm_ur thrm_hot thrm_cold thrm_or r12 / r13 ec charger alarm high / low mask register bit descriptions ac_pres mask for ac present bit bat_pres mask for battery present bit pwrfail mask for power fail bit alrminh mask for alarm inhibited bit thrm_ur mask for thermistor hot bit thrm_hot mask for battery c powering state thrm_cold mask for thermistor cold bit thrm_or mask for thermistor over-range bit
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-16 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company r14: ec battery alarm mask register this register contains the smart battery alarm message mask. when the smbus host receives a battery alarm, it ands the alarm message with the contents of r14, and if the result is not zero, the ec asserts sci to the system. this register contains the following fields. r14: ec battery alarm mask register bit definitions bit7 bit 6 bit 5 bit 4 overcharg termcharg res tempcharg bit 3 bit 2 bit 1 bit 0 termdischarg res remaincap remaintime r14: ec battery alarm mask register bit descriptions res reserved overcharg battery over charged alarm mask termcharg battery terminate charge alarm mask tempcharg battery over temperature alarm mask termdischarg battery terminate discharge alarm mask remaincap battery remaining capacity alarm mask remaintime battery remaining time alarm mask
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 7-17 smbus device access restrictions the usar ur8hc342 ACPITROLLER? does not allow access to elements of some specific smbus devices. these commands should be accomplished among the various smbus devices and should not be executed through the system. allowing these commands to be processed through the host could cause damage to some sbs elements and, as such, must be restricted. often the os or its drivers must filter these commands. a distinct advantage to the usar ur8hc342 is its ability to internally shield the sbs devices from these dangerous commands, freeing the os and drivers from this consideration. the following commands are inhibited: ? write charge current command (0x14) to smart battery charger (address 0001001). ? write charge voltage command (0x15) to smart battery charger (address 0001001). these commands are disabled because they involve data which can only be accurately calculated and reported only by the smart battery itself.
ACPITROLLER? basic ur8hc342 preliminary system management controller product smbus host controller interface usar ? a semtech company 7-18 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company this page intentionally left blank
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-1 usar ACPITROLLER? general input / output options usar ACPITROLLER? internal virtual smbus device a unique feature of the usar ACPITROLLER? is its incorporation of an internal virtual smbus device. the host can address this device through the acpi ec interface the same way it would address any external device residing on an smbus port. using smbus commands, the host can read from and write to the register space of the ACPITROLLER? the internal virtual smbus device has the seven-bit binary smbus address 0100110. it supports the following smbus protocols: usar ACPITROLLER? internal virtual smbus device supported protocols protocol action send byte set register page (byte = page number: 0 or 1) receive byte read register page (byte = page number: 0 or 1) write byte write word write block write to register space (command code = data offset, data = data to write) read byte read word read block read from register space (command code = data offset, data = data read) page 1 of the ACPITROLLER? register space contains the programmable keyboard matrix. page 0 of the ACPITROLLER? register space contains the registers in the following table.
ACPITROLLER? basic ur8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company doc8-342-tr-080 confidential 8-2 ? 1999-2000 usar ? a semtech company ACPITROLLER? registers page 0 8042 offset register no. register name read / write power-up / reset default value 00 r00 ec configuration register 0 r/w 00h 01 r01 ec configuration register 1 r/w 00h 02 r02 ec configuration register 2 r/w 00h 03 r03 ec configuration register 3 r/w 00h 04 r04 ec swi gpe enable register 0 r/w 00h 05 r05 ec swi gpe enable register 1 r/w 00h 06 r06 ec swi gpe status register 0 r/w 00h 07 r07 ec swi gpe status register 1 r/w 00h 08 r08 ec selector alarm high mask register 0 r/w 00h 09 r09 ec selector alarm high mask register 1 r/w 00h 10 r10 ec selector alarm low mask register 0 r/w 00h 11 r11 ec selector alarm low mask register 1 r/w 00h 12 r12 ec charger alarm high mask register r/w 00h 13 r13 ec charger alarm low mask register r/w 00h 14 r14 ec battery alarm mask register r/w 00h 15 r15 8042 configuration register 0 r 00h 16 r16 8042 configuration register 1 r 00h 17 r17 8042 configuration register 2 r 00h 18 r18 reserved 19 r19 gio0 data/direction register r/w 00h 20 r20-r40 reserved 41 r41 gio1 mode register r/w 00h 42 r42 gio1 data/direction register r/w 00h 43 r43 gio1 pwm1 high byte register r/w 00h 44 r44 gio1 pwm1 low byte register r/w 00h 45 r45 gio1 pwm0 high byte register r/w 00h 46 r46 gio1 pwm0 low byte register r/w 00h 47 r47 gio1 da1 data register r/w 00h 48 r48 gio1 da0 data register r/w 00h 49 r49 gio2 data/direction register r/w 00h 50 r50 gio2 ad2 data high byte register r 00h 51 r51 gio2 ad2 data low byte register r 00h 52 r52 gio2 ad1 data high byte register r 00h 53 r53 gio2 ad1 data low byte register r 00h 54 r54 gio2 ad0 data high byte register r 00h 55 r55 gio2 ad0 data low byte register r 00h 56 r56 gio3 direction register r/w 00h 57 r57 gio3 data register r/w 00h
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-3 gio0: led drivers gio0 is a 4-bit general-purpose input/output port mapped on the same pins used for the keyboard leds. the functions of the pins are determined by register r01, the ec configuration register 1. r01: ec configuration register 1 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 kkleden clleden nlleden slleden res res res res r01: ec configuration register 1 bit descriptions res reserved slleden enable gio03 as scroll lock led 1? enable as scroll lock led 0 ? general purpose i/o nlleden enable gio02 as numeric lock led 1? enable as numeric lock led 0 ? general purpose i/o clleden enable gio01 as caps lock led 1? enable as caps lock led 0 ? general purpose i/o kkleden enable gio00 as katakana led 1? enable as katakana led 0 ? general purpose i/o
ACPITROLLER? basic ur8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company doc8-342-tr-080 confidential 8-4 ? 1999-2000 usar ? a semtech company if a pin is used for general purpose i/o, the direction (input or output) and the data bit of the pin are in register r19, the gio0 data/direction register. writing to a bit whose pin is configured as an input has no effect. r19: gio0 data/direction register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir03 dir02 dir01 dir00 dat03 dat02 dat01 dat00 r19: gio0 data/direction register bit descriptions dir03 direction of pin gio03 1? output 0 ? input dir02 direction of pin gio02 1? output 0 ? input dir01 direction of pin gio01 1? output 0 ? input dir00 direction of pin gio00 1? output 0 ? input dat03 data of pin gio03 dat02 data of pin gio02 dat01 data of pin gio01 dat00 data of pin gio00
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-5 gio1: analog output for flat panel digital controls overview gio1 is a two or four channel analog output device. two pins are configurable as acpi gpe0 and gpe1 inputs. (this configuration is done in register r02; see chapter 7.) if they are configured as gpe input, then gio1 is available only as a two-pin device. all of the gio1 pins can operate in a digital input/output mode. if gio1 is configured as a two-pin device (default mode) its output can function as either a pulse width modulation (pwm) generator or a d/a converter. to select pwm or d/a mode, the oem must configure the control register defining its operating mode. if the gio1 is configured as a four-pin device, then two of the pins can be configured as pwm and two function as d/a analog outputs. the following table lists the pin names, power on default assignments as well as the function of each pin in two and four-pin modes. gio1 pin usage pin name default 2-pin analog function 4-pin analog function gio13 gio13 pwm or d/a d/a gio12 gio12 pwm or d/a d/a gpe6/gio11 gpe6 not available pwm gpe5/gio10 gpe5 not available pwm features ? includes general i/o configuration ? programmable enhanced general i/o function ? can be configured as either d/a or pwm ? two d/a or pwm channels ?
ACPITROLLER? basic ur8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company doc8-342-tr-080 confidential 8-6 ? 1999-2000 usar ? a semtech company registers register r41 determines the mode of the gio1x pins. it is not valid to assign the same pin both as d/a and to an enabled pwm channel. if a pin is not assigned as d/a, and it is not assigned to an enabled pwm channel, and it was not configured as a gpe input, then it is used for general i/o (the default). r41: gio1 mode register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res res da1 da0 pwm11 pwm1en pwm01 pwm0en r41: gio1 mode register bit descriptions res reserved da1 1? use gio13 as da1 da0 1? use gio12 as da0 pwm11 1 ? use gio13 as pwm11 0 ? use gio11 as pwm10 pwm1en 1 ? enable channel pwm1x pwm01 1 ? use gio12 as pwm01 0 ? use gio10 as pwm00 pwm0en 1 ? enable channel pwm0x
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-7 if a pin is assigned for general i/o, then the appropriate bits in r42 contain the direction and data of the i/o. writing to a bit whose pin is configured as an input has no effect. r42: gio1 data/direction register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir13 dir12 dir11 dir10 dat13 dat12 dat11 dat10 r42: gio1 data/direction register bit descriptions dir13 direction of pin gio13 1? output 0 ? input dir12 direction of pin gio12 1? output 0 ? input dir11 direction of pin gio11 1? output 0 ? input dir10 direction of pin gio10 1? output 0 ? input dat13 data of pin gio13 dat12 data of pin gio12 dat11 data of pin gio11 dat10 data of pin gio10 note note note note: only two simultaneous pwm outputs are available. pwm channel 0 can be selected to gio12 or gio10, where it is referred to as pwm01 or pwm00 respectively, and pwm channel 1 can be selected to gio13 or gio11, where it is referred to as pwm11 or pwm10 respectively.
ACPITROLLER? basic ur8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company doc8-342-tr-080 confidential 8-8 ? 1999-2000 usar ? a semtech company pwm operation for each pwm channel, the pwm generated is controlled by 14 bits, which are contained in registers r43-r46. these 14 bits are further broken down into a group of upper eight bits and a group of lower six bits. for pwm1, the upper eight bits are located in r43, and the lower six bits are located in the lower six bits of r44. . for pwm0, the upper eight bits are located in r45, and the lower six bits are located in the lower six bits of r46. the manner in which the pwm works is based on a cycle and a sub-cycle. for an oscillation frequency x in of 8mhz, the cycle period is 4096 s. each cycle is broken down into sub-cycles of 64 s. the time resolution available is 250 ns. the upper eight bits of data determine how long an ?h?-level signal is output during each sub-cycle. if the upper eight bits contain the value n, then in each sub-cycle the output signal is h for a time of n*t, where t = 250 ns, the minimum time resolution. the lower six bits allow the user to lengthen the high, for some sub-cycles, by a duration of t = 250 ns. as indicated in the table below, these bits determine which sub-cycles are lengthened. for each pulse lengthened, the leading edge of the pulse is lengthened. as a result, an accurate wave form can be duplicated without the use of complex external filters ? by changing the length of specific sub-periods instead of simply changing the global ?h? duration. for example, if the upper eight bits of the 14-bit data are 03 16 and the lower six bits are 05 16 , the length of the ?h?- level output in sub-periods t 8 , t 24 , t 32 , t 40 and t 56 is 4*t, and its length 3*t in all other sub-periods. relationship between the lower 6 bits of data and the period set by the add bit lower 6 bits of data sub-periods tm length end (m = 0 to 63) 0 0 0 0 0 0 lsb none 0 0 0 0 0 1 m = 32 0 0 0 0 1 0 m = 16, 48 0 0 0 1 0 0 m = 8, 24, 40, 56 0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60 0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 1 0 0 0 0 0 m = 1, 3, 5, 7,..., 57, 59, 61, 63 data written to the lower register is transferred to the pwm latch once during each pwm period (every 4096 s), and data written to the higher register is transferred to the pwm latch once during each sub-period (every 64 s).
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-9 the signal output to the pwm output pin corresponds to the contents of the latch. when the lower register is read, the contents of the latch are read. bit 7 of the lower register indicates whether the transfer to the pwm latch is completed; the transfer is considered complete when bit 7 is zero. d/a operations the d/a converter provides 8-bit resolution and can output to two channels. d/a conversion is initiated by writing a non-zero value into the d/a data register for the d/a channel (r47 for channel 1, r48 for channel 0). the d/a conversion results are output on the corresponding output channel, if the d/a enable flag for the channel is set to 1. the output analog voltage (?v?) is determined by value ?n? (n = decimal number) in the d/a conversion resister, as follows: v=(v ref )(n/256) (n=0255), where v ref indicates a reference voltage. note: when using a d/a converter, set vcc to 4.0v or more. reset considerations at reset, all control registers are cleared to 0 and all data registers are also cleared to 0. therefore, all pins are placed in a high impedance state. since the d/a output does not have a buffer, an external buffer should be used when connecting it to a low-impedance load.
ACPITROLLER? basic ur8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company doc8-342-tr-080 confidential 8-10 ? 1999-2000 usar ? a semtech company gio2: 3 channel 10-bit analog to digital converter overview gio2 can function as a 10-bit a/d converter or as a general purpose i/o device. to use each of the a/d channels, the oem initializes the corresponding channels as described in this section. features ? can be configured as either general i/o or a/d ? 10-bit a/d ? up to three a/d channels ? programmable enhanced general i/o function ivs2 pin usage pin name power on default function gio2:0 input gio2:1 input gio2:2/ss_sda1 input. if the internal smart selector is enabled this pin acts as the second smbus data line
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-11 registers if a pin is used for general purpose i/o, the direction (input or output) and the data bit of the pin are in register r49, the gio2 data/direction register. writing to a bit whose pin is configured as an input has no effect. r49: gio2 data/direction register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res dir22 dir21 dir20 res dat22 dat21 dat20 r49: gio2 data/direction register bit descriptions res reserved dir22 direction of pin gio22 1? output 0 ? input dir21 direction of pin gio21 1? output 0 ? input dir20 direction of pin gio20 1? output 0 ? input dat22 data of pin gio22 dat21 data of pin gio21 dat20 data of pin gio20 if the pins are configured for a/d conversion, the digital data is returned in the read-only registers r50-r55 (2 bytes of data for each a/d channel). a/d comparison voltage generator in 10-bit mode, the a/d function divides the voltage between avss and vref by 1024. the result returned signifies the number of these divisions to which the input analog voltage corresponds. thus, in 10 bit a/ d mode, with 10 bit read: vref = vref /1024 n (n=0 to 1023). in 10 bit a/d mode with 8 bit read: vref = vref / 256 n (n=0 to 255).
ACPITROLLER? basic ur8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company doc8-342-tr-080 confidential 8-12 ? 1999-2000 usar ? a semtech company gio3: general purpose i/o gio3 is a 6-pin port. the pins can be configured as acpi general purpose event inputs (gpe) (see chapter 7), or as general purpose i/o pins (the default). if a pin is used for general purpose i/o, the direction (input or output) of the pin are specified in register r56, the gio3 direction register, and the data bit of the pin is in register r57, the gio3 data register. writing to a bit whose pin is configured as an input has no effect. r56: gio3 direction register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir37 dir36 dir35 dir34 dir33 dir32 res res r56: gio3 direction register bit descriptions res reserved dir37 direction of pin gio37 1? output 0 ? input dir36 direction of pin gio36 1? output 0 ? input dir35 direction of pin gio35 1? output 0 ? input dir34 direction of pin gio34 1? output 0 ? input dir33 direction of pin gio33 1? output 0 ? input dir32 direction of pin gio32 1? output 0 ? input
ACPITROLLER? basic r8hc342 preliminary system management controller product internal virtual smbus devices usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 8-13 r57: gio3 data register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dat07 dat06 dat05 dat04 dat03 dat02 res res r57: gio3 data register bit descriptions res reserved dat37 data of pin gio37 dat36 data of pin gio36 dat35 data of pin gio35 dat34 data of pin gio34 dat33 data of pin gio33 dat32 data of pin gio32
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ACPITROLLER? basic ur8hc342 preliminary system management controller product electrical characteristics usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 9-1 electrical characteristics absolute maximum ratings (vss = 0v, ambient temperature t a is in the range t low to t high ) absolute maximum ratings parameter symbol value unit supply voltage v dd -0.3 to +7.0 v input voltage all pins except 2-9 v in -0.3 to v dd +0.3 v pins 2-9 v in -0.3 to +5.8 v output current total peak for all pins i oh (peak) i ol (peak) -80 80 ma total average for all pins i oh (avg) i ol (avg) -40 40 ma all pins except 31-34 peak for each pin i oh (peak) i ol (peak) -10 10 ma average for each pin i oh (avg) i ol (avg) -5 5 ma pins 31-34 peak for each pin i oh (peak) i ol (peak) -10 20 ma average for each pin i oh (avg) i ol (avg) -5 15 ma temperature range operating temperature t low to t high -20 to 85 oc storage temperature t stg -40 to 125 oc
usar ? a semtech company electrical characteristics ACPITROLLER? basic ur8hc342 preliminary system management controller product 9-2 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company recommended operating conditions / electrical characteristics digital section (vss = 0v, ambient temperature t a is in the range t low to t high ) recommended operating conditions/electrical characteristics, digital section parameter symbol min typ max unit supply voltage v dd 2.7 3.0 5.5 v input logic high voltage all pins except 2-9 v ih 0.8v dd v dd v pins 2-9 v ih 0.8v dd 5.5 v input logic low voltage all pins except 28 v il 0 0.2v dd v pin 28 v il 0 0.16v dd v input current v i = v ss , v dd ) i il / i ih -5.0 0 5.0 a input pull-up current (pins 56-58 / ip6-ip8, v i = v ss ) i pup -120 -10 a output voltage i oh = -1.0 ma v oh v dd ?1.0 v i ol = 1.6 ma v ol 0.4 v current consumption note 1 full speed mode (f osc =4mhz) i dd 3.5 7.0 ma reduced power mode (f osc =4mhz) i dd 750 a stop mode (interrupts active, f osc =0) i dd .1 1.0 (t a = 25oc ) 10 (t a = 85oc ) a note note note note 1 1 1 1 current consumption values do not include any loading on the output pins or analog reference current for the built-in a/d or d/a modules.
ACPITROLLER? basic ur8hc342 preliminary system management controller product electrical characteristics usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 9-3 recommended operating conditions / electrical characteristics analog section (vss = 0v, ambient temperature t a is in the range t low to t high ) recommended operating conditions/electrical characteristics, analog section parameter symbol min typ max unit analog signal ground av ss 0 v analog reference voltage av ref 2.7 v dd v dd v a/d resolution - 10 bits a/d absolute accuracy - 4 lsb a/d analog input voltage range v ia av ss av ref v a/d analog input current i ia 5.0 a analog reference current note 2 (a/d is active) i avref 200 a d/a resolution - 8 bits d/a absolute accuracy - 2.5 % d/a output impedance r o 1 2.5 4.0 kohms analog reference current note 3 (d/a is active, output = full scale) i avref 3.2 ma note note note note 2 2 2 2 since built-in a/d module consumes current only during short periods of time when a/d conversion is actually requested, the analog reference current for the built-in a/d module is not a significant contributor to the overall power consumption. note note note note 3 3 3 3 the analog reference current for the built-in d/a module correlates linearly to the output voltage. for d/a output of 0v, the analog reference current is null. for d/a outputs approaching full scale (avref ), the maximum analog reference current is indicated in this table. this current is a significant contributor to the overall power consumption. power consumption while operating the pwm channels users should consider the built-in pwm channels for generating slowly changing dc control voltages. since continuous clocking is necessary for the pwm operations, the only penalty for using the built-in pwm channels is the requirement for the chip to operate at least in the reduced power mode, with typical current consumption of 750 a.
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ACPITROLLER? basic ur8hc342 preliminary system management controller product sample schematics usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential 10-1 sample schematic
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ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix a alphakey? key numbers usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential a-1 appendix a usar alphakey? standard ps/2 key number definitions the following table lists standard ps/2 key numbers used by the usar alphakey? keyboard manager. standard ps/2 key number definitions usar key # ps/2 key # scan codes make/break scs1 key label dec hex dec hex 0 00 1 no code null key 1 01 1 29/a9 ` / ~ 2 02 2 02/82 1 / ! 3 03 3 03/83 2 /@ 4 04 4 04/84 3 / # 5 05 5 05/85 4 / $ 6 06 6 06/86 5 / % 7 07 7 07/87 6 / ^ 8 08 8 08/88 7 / & 9 09 9 09/89 8 / * 10 0a 10 0a/8a 9 / ( 11 0b 11 0b/8b 0 / ) 12 0c 12 0c/8c - / _ 13 0d 13 0d/8d = / + 14 0e 15 0e/8e backspace 15 0f 16 0f/8f tab 16 10 17 10/90 q 17 11 18 11/91 w 18 12 19 12/92 e 19 13 20 13/93 r 20 14 21 14/94 t 21 15 22 15/95 y 22 16 23 16/96 u 23 17 24 17/97 i 24 18 25 18/98 o 25 19 26 19/99 p 26 1a 27 1a/9a [ / { 27 1b 28 1b/9b ] / } 28 1c 29 2b/ab \ / | 29 1d 31 1e/9e a 30 1e 32 1f/9f s 31 1f 33 20/a0 d 32 20 34 21/a1 f 33 21 35 22/a2 g 34 22 36 23/a3 h 35 23 37 24/a4 j
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix a alphakey? key numbers usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential a-2 standard ps/2 key number definitions usar key # ps/2 key # scan codes make/break scs1 key label dec hex dec hex 36 24 38 25/a5 k 37 25 39 26/a6 l 38 26 40 27/a7 ; / : 39 27 41 28/a8 ? / ? 40 28 43 1c/9c enter 41 29 46 2c/ac z 42 2a 47 2d/ad x 43 2b 48 2e/ae c 44 2c 49 2f/af v 45 2d 50 30/b0 b 46 2e 51 31/b1 n 47 2f 52 32/b2 m 48 30 53 33/b3 , / < 49 31 54 34/b4 . / > 50 32 55 35/b5 / /? 51 33 61 39/b9 space 52 34 110 01/81 esc 53 35 75 e0 52/e0 d2 insert 54 36 76 e0 53/e0 d3 delete 55 37 79 e0 4b/e0 cb arrow left 56 38 80 e0 47/e0 c7 home 57 39 81 e0 4f/e0 cf end 58 3a 83 e0 48/e0 c8 arrow up 59 3b 84 e0 50/e0 d0 arrow down 60 3c 85 e0 49/e0 c9 page up 61 3d 86 e0 51/e0 d1 page down 62 3e 89 e0 4d/e0 cd arrow right 63 3f 100 37/b7 n. star 64 40 106 4e/ce n. + 65 41 93 4f/cf n1 / k.p.end 66 42 98 50/d0 n2 / k.p.arrow down 67 43 103 51/d1 n3 / k.p.pgdn 68 44 92 4b/cb n4 / k.p.arrow left 69 45 97 4c/cc n5 70 46 102 4d/cd n6 / k.p.arrow right 71 47 91 47/c7 n7 / k.p.home 72 48 96 48/c8 n8 / k.p.arrow up 73 49 101 49/c9 n9 / k.p.pgup 74 4a 99 52/d2 n0 / k.p.ins 75 4b 104 53/d3 n. period / k.p.del 76 4c 105 4a/ca n. - 77 4d 108 e0 1c/e0 9c n. enter 78 4e 95 e0 35/e0 b5 n. / 79 4f 112 3b/bb f1 80 50 113 3c/bc f2 81 51 114 3d/bd f3 82 52 115 3e/be f4 83 53 116 3f/bf f5
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix a alphakey? key numbers usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential a-3 standard ps/2 key number definitions usar key # ps/2 key # scan codes make/break scs1 key label dec hex dec hex 84 54 117 40/c0 f6 85 55 118 41/c1 f7 86 56 119 42/c2 f8 87 57 120 43/c3 f9 88 58 121 44/c4 f10 89 59 122 57/d7 f11 90 5a 123 58/d8 f12 91 5b 44 2a/aa l. shift 92 5c 57 36/b6 r. shift 93 5d 60 38/b8 l. alt 94 5e 62 e0 38/e0 b8 r. alt 95 5f 58 1d/9d l. ctrl 96 60 64 e0 1d/e0 9d r. ctrl 97 61 30 3a/ba caps lock 98 62 90 45/c5 num lock 99 63 125 46/c6 scroll lock 100 64 124 e0 2a e0 37 / e0 b7 e0 aa print scr / sysreq 101 65 126 e1 1d 45 e1 9d c5 pause / break 102 66 e0 5b/e0 db left win 103 67 e0 5c/e0 dc right win 104 68 e0 5d/e0 dd win application 105 69 ff overrun error 106 6a no code function key 107 6b no code sticky key 108 6c e0 5e/e0 de power event 109 6d e0 5f/e0 df sleep event 110 6e e0 63/e0 e3 wake event 111 6f 70/f0 katakana 112 70 7b/fb nfer, f20 113 71 79/f9 xfer, f17 114 72 7d/fd yen, f23 115 73 73/f3 / / _ 116 74 5b/db f13 117 75 5c/dc f14 118 76 5d/dd f15 119 77 63/e3 f16 120 78 65/e5 f18 121 79 66/e6 f19 122 7a 68/e8 f21 123 7b 69/e9 f22 124 7c 6b/eb f24 125? 127 7d ? 7f reserved
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix a alphakey? key numbers usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential a-4 this page intentionally left blank
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix b alphakey ? keyboard matrix usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential b-1 appendix b usar alphakey? default matrix & layout usar alphakey? default scan matrix columns rows matrix ram offset usar key number qwerty layout key label numpad layout key label fn layout key label row 0 00 0 row 1 01 0 row 2 02 0 row 3 03 0 row 4 04 0 row 5 05 0 row 6 06 0 row 7 07 106 function function function col 0 row 0 08 0 row 1 09 0 row 2 0a 0 row 3 0b 0 row 4 0c 0 row 5 0d 102 left win left win left win row 6 0e 0 col 1 row 7 0f 0 row 0 10 15 tab tab tab row 1 11 97 caps lock caps lock caps lock row 2 12 2 1 / ! 1 / ! 1 / ! row 3 13 30 s s s row 4 14 41 z z z row 5 15 29 a a a row 6 16 16 q q q col 2 row 7 17 52 escape escape escape row 0 18 0 row 1 19 0 row 2 1a 0 row 3 1b 0 row 4 1c 94 right alt right alt right alt row 5 1d 0 row 6 1e 0 col 3 row 7 1f 93 left alt left alt left alt
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix b alphakey? keyboard matrix usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential b-2 usar alphakey? default scan matrix columns rows matrix ram offset usar key number qwerty layout key label numpad layout key label fn layout key label row 0 20 79 f1 f1 f1 row 1 21 80 f2 f2 f2 row 2 22 81 f3 f3 f3 row 3 23 18 e e e row 4 24 31 d d d row 5 25 17 w w w row 6 26 3 2 / @ 2 / @ 2 / @ col 4 row 7 27 42 x x x row 0 28 141 8 / * 8 / up arrow 8 / * row 1 29 140 9 / ( 9 / pgup 9 / ( row 2 2a 136 | 5 | row 3 2b 48 , / < , / < , / < row 4 2c 51 space space space row 5 2d 134 k 2 / dn arrow k row 6 2e 137 u 4 / left arrow u col 5 row 7 2f 135 m 0 / ins m row 0 30 84 f6 f6 f6 row 1 31 4 3 / # 3 / # 3 / # row 2 32 5 4 / $ 4 / $ 4 / $ row 3 33 32 f f f row 4 34 43 c c c row 5 35 19 r r r row 6 36 6 5 / % 5 / % 5 / % col 6 row 7 37 82 f4 f4 f4 row 0 38 87 f9 f9 f9 row 1 39 83 f5 f5 f5 row 2 3a 7 6 / ^ 6 / ^ 6 / ^ row 3 3b 44 v v v row 4 3c 45 b b b row 5 3d 33 g g g row 6 3e 20 t t t col 7 row 7 3f 85 f7 f7 f7 row 0 40 88 f10 f10 f10 row 1 41 89 f11 f11 f11 row 2 42 86 f8 f8 f8 row 3 43 46 n n n row 4 44 34 h h h row 5 45 21 y y y row 6 46 142 7 / & 7 / home 7 / & col 8 row 7 47 138 j 1 / end j
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix b alphakey ? keyboard matrix usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential b-3 usar alphakey? default scan matrix columns rows matrix ram offset usar key number qwerty layout key label numpad layout key label fn layout key label row 0 48 90 f12 f12 f12 row 1 49 143 0 / ) * 0 / ) row 2 4a 133 o 6 / rt arrow o row 3 4b 145 . / > . / del . / > row 4 4c 0 row 5 4d 0 row 6 4e 129 l 3 / pgdn nfer 1 , f20 col 9 row 7 4f 139 num lock num lock scroll lock row 0 50 101 pause / break pause / break pause / break row 1 51 13 = / + = / + = / + row 2 52 27 ] / } ] / } ] / } row 3 53 28 \ / | \ / | \ / | row 4 54 0 row 5 55 0 row 6 56 26 [ / { [ / { [ / { col 10 row 7 57 1 ` / ~ ` / ~ ` / ~ row 0 58 14 back space back space back space row 1 59 146 down arrow down arrow pgdn row 2 5a 147 up arrow up arrow pgup row 3 5b 39 ? / ? ? / ? ? / ? row 4 5c 104 win appl. win appl. win appl. row 5 5d 40 enter enter enter row 6 5e 0 col 11 row 7 5f 13 insert insert insert row 0 60 0 row 1 61 0 row 2 62 0 row 3 63 103 rwin rwin rwin row 4 64 0 row 5 65 0 row 6 66 0 col 12 row 7 67 0 row 0 68 148 right arrow num lock end row 1 69 149 left arrow left arrow home row 2 6a 150 delete delete sysrq row 3 6b 144 / / ? / / / ? row 4 6c 0 row 5 6d 130 ; / : + ; / : row 6 6e 151 p - p col 13 row 7 6f 12 - / _ - / _ - / _
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix b alphakey? keyboard matrix usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential b-4 usar alphakey? default scan matrix columns rows matrix ram offset usar key number qwerty layout key label numpad layout key label fn layout key label row 0 70 0 row 1 71 95 left ctrl left ctrl left ctrl row 2 72 0 row 3 73 0 row 4 74 0 row 5 75 0 row 6 76 96 right ctrl right ctrl right ctrl col 14 row 7 77 0 row 0 78 91 left shift page up page up row 1 79 0 row 2 7a 92 right shift ] / } ] / } row 3 7b 0 row 4 7c 0 row 5 7d 0 row 6 7e 0 row 7 7f 0 col 15
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential c-1 appendix c standard smbus registers protocol register, smb_prtcl this register determines the type of smbus transaction generated on the smbus. in addition to indicating the protocol type to the smbus host controller, a write to this register initiates the transaction on the smbus. bit descriptions for protocol register smb_prtcl bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 protocol the values of the protocol are as follows: protocol definitions for protocol register smb_prtcl value (hex) meaning 00 controller not in use 01 reserved 02 write quick command 03 read quick command 04 send byte 05 receive byte 06 write byte 07 read byte 08 write word 09 read word 0a block write 0b block read 0c process call when the os initiates a new command such as write to the smb_prtcl register, the smbus controller first updates the smb_sts register and then clears the smb_prtcl register. after the smb_prtcl register is cleared, the host controller query value is raised.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company c-2 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company status register, smb_sts this register indicates general status on the smbus. this includes smbus host controller command completion status, alarm received status, and error detection status (the error codes are defined later in this section). whenever a new command is issued using a write to the protocol register (smb_prtcl), bits 7 and 2 of this register are reset to 0. this register is always written with the error code before clearing the protocol register. the smbus host controller query event (that is, an smbus host controller interrupt) is raised after the clearing of the protocol register. note: the os driver must ensure the alrm bit is cleared after it has been serviced by writing ?00? to the smb_sts register. status register smb_sts bit descriptions bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 done alrm res res res status res res status register smb_sts bit descriptions res reserved. done when set to 1, indicates the last command has completed and no error. alrm when set to 1, indicates an smbus alarm message has been received. status when set to 1, indicates smbus communication status for one of the reasons listed in the following table. the following table shows smbus status codes. smbus status codes status code name description 00h smbus ok indicates the transaction has been successfully completed. 07h smbus unknown failure indicates failure because of an unknown smbus error. 10h smbus device address not acknowledged indicates the transaction failed because the slave device address was not acknowledged. 11h smbus device error detected indicates the transaction failed because the slave device signaled an error condition. 12h smbus device command access denied indicates the transaction failed because the smbus host does not allow the specific command for the device being addressed. for example, the smbus host might not allow a caller to adjust the smart battery charger's output. 13h smbus unknown error indicates the transaction failed because the smbus host encountered an unknown error.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential c-3 smbus status codes status code name description 17h smbus device access denied indicates the transaction failed because the smbus host does not allow access to the device addressed. for example, the smbus host might not allow a caller to directly communicate with an smbus device that controls the system's power planes. 18h smbus timeout indicates the transaction failed because the smbus host detected a timeout on the bus. 19h smbus host unsupported protocol indicates the transaction failed because the smbus host does not support the requested protocol. 1ah smbus busy indicates that the transaction failed because the smbus host reports that the smbus is presently busy with some other transaction. for example, the smart battery might be sending charging information to the smart battery charger. all other status codes are reserved. address register, smb_addr this register contains the 7-bit address to be generated on the smbus. this is the first byte to be sent on the smbus for all of the different protocols. smb_addr address register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address (a6:a0) res res reserved address 7-bit smbus address command register, smb_cmd this register contains the command byte to be sent to the target device on the smbus and is used for all of the protocols except for receive byte, read quick command, and write quick command. for those protocols, the value in smb_cmd has no effect. smb_cmd command register bit definitions bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 command
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company c-4 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company data register array, smb_data[i], i=0-31 this bank of registers contains the remaining bytes to be sent or received in any of the different protocols that can be run on the smbus. the smb_data registers are defined on a per-protocol basis and, as such, provide efficient use of register space. smb_data[i] data register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data block count register, smb_bcnt this register contains the block count, used in the block read and block write protocols. smb_bcnt block count register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res bcnt res reserved bcnt block count alarm address register, smb_alrm_addr this register contains the source address of an alarm message received by the host controller from the smbus master that initiated the alarm. the address indicates the slave address of the device on the smbus that initiated the alarm message. the status of the alarm message is contained in the smb_alrm_datax registers. once an alarm message has been received, the smbus host controller must clear the alrm status bits to receive further alarm messages.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential c-5 the os driver does not read the alarm address and alarm data registers until the alarm status bit is set. the os driver then reads the three bytes, and clears the alarm status bit to indicate that the alarm registers are now available for the next event. smb_bcnt block count register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address (a6:a0) res res reserved address 7-bit slave address (a6:a0) of the smbus device that initiated the alarm message alarm data registers, smb_alrm_data[0], smb_alrm_data[1] these registers contain the two data bytes of an alarm message received by the host controller, from the smbus master that initiated the alarm. these data bytes indicate the specific reason for the alarm message, to allow the os to take corrective action. once an alarm message has been received, the smbus host controller must clear the alrm status bits to receive further alarm messages. smb_alrm_data alarm data register bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data (d7:0)
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company c-6 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company standard smbus protocol protocol description all registers should be written with the appropriate values before writing the protocol value that starts the smbus transaction. all transactions can be completed in one pass. write quick data sent: ? smb_addr: address of smbus device. ? smb_prtcl: write 0x02 to initiate quick write protocol. data returned: ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. read quick data sent: ? smb_addr: address of smbus device. ? smb_prtcl: write 0x03 to initiate quick read protocol. data returned: ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. send byte data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_prtcl: write 0x04 to initiate send byte protocol. data returned: ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential c-7 receive byte data sent: ? smb_addr: address of smbus device. ? smb_prtcl: write 0x05 to initiate receive byte protocol. data returned: ? smb_data[0]: data byte received. ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. write byte data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_data[0]: data byte to be sent. ? smb_prtcl: write 0x06 to initiate write byte protocol. data returned: ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. read byte data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_prtcl: write 0x07 to initiate read byte protocol. data returned: ? smb_data[0]: data byte received. ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company c-8 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company write word data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_data[0]: low data byte to be sent. ? smb_data[1]: high data byte to be sent. ? smb_prtcl: write 0x08 to initiate write word protocol. data returned: ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. read word data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_prtcl: write 0x09 to initiate read word protocol. data returned: ? smb_data[0]: low data byte received. ? smb_data[1]: high data byte received. ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. write block data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_data[0- data bytes to write (1-32). ? smb_bcnt: number of data bytes (1-32) to be sent. ? smb_prtcl: write 0x0a to initiate write block protocol. data returned: ? smb_prtcl: 0x00 to indicate command completion. ? smb_sts: status code for transaction.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company ? 1999-2000 usar ? a semtech company doc8-342-tr-080 confidential c-9 read block data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_prtcl: write 0x0b to initiate read block protocol. data returned: ? smb_bcnt: number of data bytes (1-32) received. ? smb_data[0:31 data bytes received (1-32). ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion. process call data sent: ? smb_addr: address of smbus device. ? smb_cmd: command byte to be sent. ? smb_data[0]: low data byte to be sent. ? smb_data[1]: high data byte to be sent. ? smb_prtcl: write 0x0c to initiate process call protocol. data returned: ? smb_data[0]: low data byte received. ? smb_data[1]: high data byte received. ? smb_sts: status code for transaction. ? smb_prtcl: 0x00 to indicate command completion.
ACPITROLLER? basic ur8hc342 preliminary system management controller product appendix c standard smbus registers and protocol usar ? a semtech company c-10 doc8-342-tr-080 confidential ? 1999-2000 usar ? a semtech company this page intentionally left blank
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